Historical Perspective of System in Package (SiP)

"Moore Stress" calls for technology and architecture innovation, and System in Package (SiP) is critical to address the challenge. System in Package is a generalization of System on Chip. As such, SiP is a giant chip rather than a miniaturized Printed Circuit Board (PCB). SiP using Wafer Level Package (WLP) enables performance efficient and cost effective integration of DRAM and logic. SiP with Integrated Passive Devices (IPD) provides high quality and low energy platforms for mixed signal and RF circuits. Billions of chips are shipped each year using SiP due to ultra small form factor with very low power consumption for smartphones, smart wearable devices such as smart watches, and Internet of Things (IoT). From editing the book “Multichip Modules” in 1992 to providing leadership for the IEEE Multi-Chip Module Conference (MCMC) from 1992 to 1997, Professor Ernest Kuh made profound contributions to the field of System in Package, particularly in design, analytical methods, and extensively toward CAD tools for SiP. His influence and vision led to the special session on “System in Package” at ASP-DAC in 2000, where the term “System in Package (SiP)” was used in a conference and in publications for the first time and is now widely used in the industry.

[1]  Minqing Liu,et al.  Modeling and analysis of integrated spiral inductors for RF system-in-package , 2000, ASP-DAC '00.

[2]  Wenjian Yu,et al.  Analysis and Optimization of Low-Power Passive Equalizers for CPU–Memory Links , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[3]  Ernest S. Kuh,et al.  Pade approximation applied to transient simulation of lossy coupled transmission lines , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[4]  Ernest S. Kuh,et al.  Exact moment matching model of transmission lines and application to interconnect delay estimation , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Ernest S. Kuh,et al.  A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies , 1996, Proceedings 1996 IEEE Multi-Chip Module Conference (Cat. No.96CH35893).

[6]  R.R. Johnson.  Multichip modules: next-generation packages , 1990, IEEE Spectrum.

[7]  Albert Lin.  Taiwan foundry for system-in-package (SIP) , 2000, ASP-DAC '00.

[8]  Dongsheng Wang,et al.  A performance-driven MCM router with special consideration of crosstalk reduction , 1998, Proceedings Design, Automation and Test in Europe.

[9]  Ernest S. Kuh,et al.  Moment models of general transmission lines with application to MCM interconnect analysis , 1995, Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95).

[10]  Dongsheng Wang,et al.  A new timing-driven multilayer MCM/IC routing algorithm , 1997, Proceedings 1997 IEEE Multi-Chip Module Conference.

[11]  Ren-Song Tsay,et al.  System partitioning for multi-chip modules under timing and capacity constraints , 1992, Proceedings 1992 IEEE Multi-Chip Module Conference MCMC-92.

[12]  Wayne Wei-Ming Dai,et al.  Design and analysis of area-IO DRAM/logic integration with system-in-a-package (SiP) , 2005, Sixth international symposium on quality electronic design (isqed'05).

[13]  King L. Tai.  System-in-package (SIP): challenges and opportunities , 2000, ASP-DAC '00.

[14]  T. Ohtsuki,et al.  Recent advances in VLSI layout , 1990, Proc. IEEE.

[15]  Ren-Song Tsay,et al.  Timing-driven system partitioning by constraints decoupling method , 1993, Proceedings 1993 IEEE Multi-Chip Module Conference MCMC-93.

[16]  Jun-Fa Mao,et al.  Fast simulation and sensitivity analysis of lossy transmission lines by the method of characteristics , 1997 .