A high-speed CMOS incrementer/decrementer

A new circuit structure for the incrementer/decrementer is proposed in this paper. The design concept is similar to that used in our previously proposed high-speed priority encoder. This circuit is especially suitable for constructing a long incrementer/decrementer because it owns a multiple look-ahead structure and utilizes the dynamic CMOS circuit. For a 32-bit incrementer/decrementer, the proposed design can achieve a speed improvement as large as 3.0 times as compared to the adder-based design. The power-delay-product performance of the proposed design is also the best among all the incrementer/decrementers. And the new design also requires much fewer transistors than previous designs.

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