A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator

In this paper, a compact inductor-less PLL using multiple coupled rings oscillator is presented. Sub-sampling technique with soft loop gain switching is applied to reduce the in-band phase noise. As a result, the loop bandwidth can be widened, which suppresses the phase noise from ring oscillator as well. Fractional-N mode is implemented by utilizing the multiple phase outputs inherently generated by the ring VCO. Using multiple rings instead of one allows generating more phases for finer frequency resolution without decreasing oscillation frequency. The coupled multi-ring oscillator with proper phase shift also achieves reduced phase noise comparing to their single-ring counterpart. The PLL was implemented in a 0.13um CMOS technology, consuming 19 mW from a 1.3 V power supply. The measured largest in-band fractional spur at 2.08 MHz is −42 dBc. The measured integrated jitters were 571 fs and 690 fs around 1.2GHz output in integer mode and fractional mode respectively, achieving a FoM of −230 dB.

[1]  Ahmed Elkholy,et al.  A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method , 2015, IEEE Journal of Solid-State Circuits.

[2]  Ruixin Wang,et al.  A 1∼1.5 GHz capacitive coupled inductor-less multi-ring oscillator with improved phase noise , 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

[3]  Giovanni Marucci,et al.  21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[4]  Ping-Ying Wang,et al.  10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[5]  Jaehyouk Choi,et al.  10.7 A 185fsrms-integrated-jitter and −245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[6]  Eric A. M. Klumperink,et al.  Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector , 2010, IEEE Journal of Solid-State Circuits.

[7]  Peter R. Kinget,et al.  A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.