Optimization and Modeling of FPGA Circuitry in Advanced Process Technology

Optimization and Modeling of FPGA Circuitry in Advanced Process Technology Charles Chiasson Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2013 We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of “gate boosting”. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%.

[1]  John K. Ousterhout.  Switch-Level Delay Models for Digital MOS VLSI , 1984, 21st Design Automation Conference Proceedings.

[2]  John P. Fishburn,et al.  TILOS: A posynomial programming approach to transistor sizing , 2003, ICCAD 2003.

[3]  David M. Lewis,et al.  Architectural enhancements in Stratix V™ , 2013, FPGA '13.

[4]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[5]  Anthony J. Yu,et al.  Directional and single-driver wires in FPGA interconnect , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[6]  Anil Telikepalli.  Power vs. Performance: The 90 nm Inflection Point , 2006 .

[7]  Philip N. Strenski,et al.  Gradient-based optimization of custom circuits using a static-timing formulation , 1999, DAC '99.

[8]  Charlie Chung-Ping Chen,et al.  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, ICCAD.

[9]  Alberto Sangiovanni-Vincentelli,et al.  Optimization-based transistor sizing , 1988, IEEE J. Solid State Circuits.

[10]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[11]  Jonathan Rose,et al.  Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Sung-Mo Kang,et al.  An exact solution to the transistor sizing problem for CMOS circuits using convex optimization , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Vaughn Betz,et al.  Automatic generation of FPGA routing architectures from high-level descriptions , 2000, FPGA '00.

[14]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  C. S. Chen,et al.  Characterization and simulation of NMOS pass transistor reliability for FPGA routing circuits , 2013, 2013 IEEE International Conference on Microelectronic Test Structures (ICMTS).

[16]  Vaughn Betz,et al.  Comparing FPGA vs. custom cmos and the impact on processor microarchitecture , 2011, FPGA '11.

[17]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Andrew R. Conn,et al.  JiffyTune: circuit optimization using time-domain sensitivities , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Peter Y. K. Cheung,et al.  FPGA Architecture Optimization Using Geometric Programming , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  David Lewis,et al.  Using Sparse Crossbars within LUT Clusters , 2001 .

[21]  Wayne Luk,et al.  An analytical model describing the relationships between logic architecture and FPGA density , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[22]  Kenneth B. Kent,et al.  VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2011, TRETS.

[23]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[24]  Keshab K. Parhi,et al.  Fast and exact transistor sizing based on iterative relaxation , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Zvonko G. Vranesic,et al.  Modelling Routing Delays in SRAM-based FPGAs , 1993 .

[26]  Vaughn Betz,et al.  A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs , 2010, FPGA '10.

[27]  Kenneth B. Kent,et al.  The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.

[28]  Abdulazim Amouri,et al.  Investigation of NBTI and PBTI induced aging in different LUT implementations , 2011, 2011 International Conference on Field-Programmable Technology.

[29]  Sachin S. Sapatnekar,et al.  A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates] , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  W. C. Elmore.  The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[31]  H.-S. Philip Wong,et al.  Efficient FPGAs using nanoelectromechanical relays , 2010, FPGA '10.

[32]  M. Anis,et al.  "Impact of Technology Scaling on CMOS Logic Styles", IEEE Transactions On Circuits and Systems-II , 2002 .

[33]  D. Lewis,et al.  Process technology implications for FPGAs (Invited Paper) , 2012, 2012 International Electron Devices Meeting.

[34]  S. Sapatnekar,et al.  A New Class of Convex Functions for Delay Modeling and Its Application to the Transistor Sizing Problem , 2000 .

[35]  Shahriar Mirabbasi,et al.  Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays , 2008, J. Signal Process. Syst..

[36]  Jason Cong,et al.  Buffered Steiner tree construction with wire sizing for interconnect layout optimization , 1996, ICCAD 1996.

[37]  Abdulazim Amouri,et al.  Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs , 2012, 2012 International Conference on Field-Programmable Technology.

[38]  Vaughn Betz,et al.  Routing and Logic Architecture , 2003 .

[39]  Steven J. E. Wilton,et al.  A New Switch Block for Segmented FPGAs , 1999, FPL.

[40]  Guy Lemieux,et al.  Design of interconnection networks for programmable logic , 2003 .

[41]  Jonathan Rose,et al.  Improving FPGA routing architectures using architecture and CAD interactions , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[42]  Guy Lemieux,et al.  Circuit design of routing switches , 2002, FPGA '02.

[43]  Jonathan Rose,et al.  Modeling routing demand for early-stage FPGA architecture development , 2008, FPGA '08.

[44]  Vaughn Betz,et al.  The Stratix II logic and routing architecture , 2005, FPGA '05.