Ultra-low swing CMOS transceiver for 2.5-D integrated systems

This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4∗ higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.

[1]  Manoj Sachdev,et al.  A low-power reduced swing global clocking methodology , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Eby G. Friedman,et al.  Three-dimensional Integrated Circuit Design , 2008 .

[3]  Saeid Nooshabadi,et al.  CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  C. Svensson.  Optimum voltage swing on on-chip and off-chip interconnects , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[5]  Dennis Sylvester,et al.  High performance level conversion for dual V/sub DD/ design , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  P.A. Beerel,et al.  Low swing signaling using a dynamic diode-connected driver , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[7]  Baher Haroun,et al.  A novel reduced swing CMOS bus interface circuit for high speed low power VLSI systems , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[8]  Saeid Nooshabadi,et al.  Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[9]  Emre Salman,et al.  Low swing TSV signaling using novel level shifters with single supply voltage , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[10]  Lee-Sup Kim,et al.  High-speed and low-swing on-chip bus interface using threshold voltage swing driver and dual sense amplifier receiver , 2000, Proceedings of the 26th European Solid-State Circuits Conference.

[11]  George Varghese,et al.  Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Kwyro Lee,et al.  High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[13]  Christopher George,et al.  Process technology scaling in an increasingly interconnect dominated world , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.