A comprehensive study and analysis on SAT-solvers: advances, usages and achievements

Boolean satisfiability (SAT) has been studied for the last twenty years. Advances have been made allowing SAT solvers to be used in many applications including formal verification of digital designs. However, performance and capacity of SAT solvers are still limited. From the practical side, many of the existing applications based on SAT solvers use them as blackboxes in which the problem is translated into a monolithic conjunctive normal form instance and then throw it to the SAT solver with no interaction between the application and the SAT solver. This paper presents a comprehensive study and analysis of the latest developments in SAT-solver and new approaches that used in branching heuristics, Boolean constraint propagation and conflict analysis techniques during the last two decade. In addition, the paper provides the most effective techniques in using SAT solvers as verification techniques, mainly model checkers, to enhance the SAT solver performance, efficiency and productivity. Moreover, the paper presents the remarkable accomplishments and the main challenges facing SAT-solver techniques and contrasts between different techniques according to their efficiency, algorithms, usage and feasibility.

[1]  Paul B. Jackson,et al.  Clause Form Conversions for Boolean Circuits , 2004, SAT (Selected Papers.

[2]  Weimin Wu,et al.  ASIG: An all-solution SAT solver for CNF formulas , 2009, 2009 11th IEEE International Conference on Computer-Aided Design and Computer Graphics.

[3]  Robert K. Brayton,et al.  DAG-aware AIG rewriting: a fresh look at combinational logic synthesis , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[4]  Gilles Audemard,et al.  Predicting Learnt Clauses Quality in Modern SAT Solvers , 2009, IJCAI.

[5]  Adnan Darwiche,et al.  A Lightweight Component Caching Scheme for Satisfiability Solvers , 2007, SAT.

[6]  Akira Fukuda,et al.  A Survey of Acceleration Techniques for SMT-Based Bounded Model Checking , 2013, 2013 International Conference on Computer Sciences and Applications.

[7]  Wilhelm Ackermann,et al.  Solvable Cases Of The Decision Problem , 1954 .

[8]  Per Bjesse,et al.  DAG-aware circuit compression for formal verification , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[9]  Fausto Giunchiglia,et al.  SAT-Based Decision Procedures for Classical Modal Logics , 2004, Journal of Automated Reasoning.

[10]  Miroslav N. Velev,et al.  Using Automatic Case Splits and Efficient CNF Translation to Guide a SAT-solver when Formally Verifying Out-Of-Order Processors , 2004, AI&M.

[11]  Olivier Roussel,et al.  A Translation of Pseudo Boolean Constraints to SAT , 2006, J. Satisf. Boolean Model. Comput..

[12]  Sharad Malik,et al.  New Features of the SAT ’ 04 versions of zChaff Zhaohui , 2004 .

[13]  Lawrence Ryan.  Efficient algorithms for clause-learning SAT solvers , 2004 .

[14]  Mizuhito Ogawa,et al.  SAT and SMT: Their Algorithm Designs and Applications , 2013, 2013 20th Asia-Pacific Software Engineering Conference (APSEC).

[15]  Adam Naumowicz.  SAT-Enhanced Mizar Proof Checking , 2014, CICM.

[16]  Hantao Zhang,et al.  SATO: An Efficient Propositional Prover , 1997, CADE.

[17]  Bernd Becker,et al.  Using MaxBMC for Pareto-optimal circuit initialization , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[18]  Masahiro Fujita,et al.  Model Checking Based on Sequential ATPG , 1999, CAV.

[19]  Kenneth L. McMillan,et al.  Interpolation and SAT-Based Model Checking , 2003, CAV.

[20]  Wolfgang Küchlin,et al.  Parallel propositional satisfiability checking with distributed dynamic learning , 2003, Parallel Comput..

[21]  Hans van Maaren,et al.  Parallel SAT Solving using Bit-level Operations , 2008, J. Satisf. Boolean Model. Comput..

[22]  Karem A. Sakallah,et al.  Pueblo: A Hybrid Pseudo-Boolean SAT Solver , 2006, J. Satisf. Boolean Model. Comput..

[23]  Wei Wu,et al.  Double Configuration Checking in Stochastic Local Search for Satisfiability , 2014, AAAI.

[24]  Konstantin Korovin,et al.  iProver - An Instantiation-Based Theorem Prover for First-Order Logic (System Description) , 2008, IJCAR.

[25]  J. Freeman.  Improvements to propositional satisfiability search algorithms , 1995 .

[26]  Ian P. Gent.  Proceedings of the 15th international conference on Principles and practice of constraint programming , 2009 .

[27]  Ewald Speckenmeyer,et al.  A fast parallel SAT-solver — efficient workload balancing , 2005, Annals of Mathematics and Artificial Intelligence.

[28]  Dhiraj K. Pradhan,et al.  NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances , 2004, SAT.

[29]  Josep Argelich,et al.  Exact Max-SAT solvers for over-constrained problems , 2006, J. Heuristics.

[30]  Gilles Audemard,et al.  Improving Glucose for Incremental SAT Solving with Assumptions: Application to MUS Extraction , 2013, SAT.

[31]  Sharad Malik,et al.  Boolean Satisfiability Solvers and Their Applications in Model Checking , 2015, Proceedings of the IEEE.

[32]  Armando Tacchella,et al.  Theory and Applications of Satisfiability Testing: 6th International Conference, Sat 2003, Santa Margherita Ligure, Italy, May 5-8 2003: Selected Revised Papers (Lecture Notes in Computer Science, 2919) , 2004 .

[33]  J. P. Marques,et al.  GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .

[34]  Niklas Sörensson,et al.  Translating Pseudo-Boolean Constraints into SAT , 2006, J. Satisf. Boolean Model. Comput..

[35]  Daniel Sheridan,et al.  The Optimality of a Fast CNF Conversion and its Use with SAT , 2004, SAT.

[36]  Lakhdar Sais,et al.  Learning for Dynamic Subsumption , 2009, 2009 21st IEEE International Conference on Tools with Artificial Intelligence.

[37]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[38]  David L. Dill,et al.  Automatic verification of Pipelined Microprocessor Control , 1994, CAV.

[39]  A. Kuehlmann,et al.  A fast pseudo-Boolean constraint solver , 2005, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[40]  Peter J. Stuckey,et al.  Cache Conscious Data Structures for Boolean Satisfiability Solvers , 2009, J. Satisf. Boolean Model. Comput..

[41]  Rolf Drechsler,et al.  Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization , 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

[42]  Randal E. Bryant,et al.  Boolean satisfiability with transitivity constraints , 2000, TOCL.

[43]  Thierry Boy de la Tour.  An Optimality Result for Clause Form Translation , 1992, J. Symb. Comput..

[44]  Dian Zhou,et al.  Enhance SAT conflict analysis for model checking , 2009, 2009 IEEE 8th International Conference on ASIC.

[45]  Holger H. Hoos,et al.  An adaptive noise mechanism for walkSAT , 2002, AAAI/IAAI.

[46]  Joël Ouaknine,et al.  Deciding Bit-Vector Arithmetic with Abstraction , 2007, TACAS.

[47]  Maria Luisa Bonet,et al.  Towards Industrial-Like Random SAT Instances , 2009, IJCAI.

[48]  Olga Tveretina,et al.  EufDpll - A Tool to Check Satisfiability of Equality Logic Formulas , 2009, Electron. Notes Theor. Comput. Sci..

[49]  Armin Biere,et al.  A survey of recent advances in SAT-based formal verification , 2005, International Journal on Software Tools for Technology Transfer.

[50]  Orna Grumberg,et al.  Interpolation-sequence based model checking , 2009, 2009 Formal Methods in Computer-Aided Design.

[51]  Martín Rodríguez Vega.  Analyzing toys models of Arabidopsis and Drosphila using Z3 SMT-LIB , 2014, Sensing Technologies + Applications.

[52]  Norbert Manthey.  Solver submission of riss 1 . 0 to the SAT Competition 2011 , 2011 .

[53]  Eugene Goldberg,et al.  BerkMin: A Fast and Robust Sat-Solver , 2002 .

[54]  Rolf Drechsler,et al.  Test Pattern Generation using Boolean Proof Engines , 2009 .

[55]  Ofer Strichman,et al.  Pruning Techniques for the SAT-Based Bounded Model Checking Problem , 2001, CHARME.

[56]  Fahiem Bacchus,et al.  Effective Preprocessing with Hyper-Resolution and Equality Reduction , 2003, SAT.

[57]  Daniel Kroening,et al.  Interpolating Quantifier-Free Presburger Arithmetic , 2010, LPAR.

[58]  Helmut Veith,et al.  Automated Abstraction Refinement for Model Checking Large State Spaces Using SAT Based Conflict Analysis , 2002, FMCAD.

[59]  Predrag Janicic,et al.  Formal Correctness Proof for DPLL Procedure , 2010, Informatica.

[60]  Kaile Su,et al.  Local search for Boolean Satisfiability with configuration checking and subscore , 2013, Artif. Intell..

[61]  Matthew L. Ginsberg,et al.  Inference methods for a pseudo-boolean satisfiability solver , 2002, AAAI/IAAI.

[62]  Russell Impagliazzo,et al.  On the Exact Complexity of Evaluating Quantified k-CNF , 2010, Algorithmica.

[63]  Roope Kaivola,et al.  Relational STE and theorem proving for formal verification of industrial circuit designs , 2013, 2013 Formal Methods in Computer-Aided Design.

[64]  Nikolaj Bjørner,et al.  Z3: An Efficient SMT Solver , 2008, TACAS.

[65]  Otmane Aït Mohamed,et al.  MDG-SAT: an automated methodology for efficient safety checking , 2012, Int. J. Crit. Comput. Based Syst..

[66]  Marius Thomas Lindauer,et al.  AutoFolio: An Automatically Configured Algorithm Selector , 2015, J. Artif. Intell. Res..

[67]  Randal E. Bryant,et al.  Exploiting Positive Equality in a Logic of Equality with Uninterpreted Functions , 1999, CAV.

[68]  Robert P. Kurshan,et al.  An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment , 2005, CHARME.

[69]  Panagiotis Manolios,et al.  Efficient Circuit to CNF Conversion , 2007, SAT.

[70]  Kevin Leyton-Brown,et al.  SATzilla: Portfolio-based Algorithm Selection for SAT , 2008, J. Artif. Intell. Res..

[71]  Hector J. Levesque,et al.  A New Method for Solving Hard Satisfiability Problems , 1992, AAAI.

[72]  Julian Stecklina,et al.  A short overview on modern parallel SAT-solvers , 2011, 2011 International Conference on Advanced Computer Science and Information Systems.

[73]  El Mostapha Aboulhamid,et al.  An Efficient Hardware Implementation of a SAT Problem Solver on FPGA , 2013, 2013 Euromicro Conference on Digital System Design.

[74]  Dirk Nowotka,et al.  Communication in Massively-Parallel SAT Solving , 2014, 2014 IEEE 26th International Conference on Tools with Artificial Intelligence.

[75]  Andreas Bauer,et al.  Tool-support for the analysis of hybrid systems and models , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[76]  Siert Wieringa,et al.  Tarmo: A Framework for Parallelized Bounded Model Checking , 2009, PDMC.

[77]  Mary Sheeran,et al.  Checking Safety Properties Using Induction and a SAT-Solver , 2000, FMCAD.

[78]  Philippe Codognet,et al.  A Survey of Parallel Local Search for SAT , 2013 .

[79]  Cesare Tinelli,et al.  Satisfiability Modulo Theories , 2021, Handbook of Satisfiability.

[80]  Thomas Stützle,et al.  Local Search Algorithms for SAT: An Empirical Evaluation , 2000, Journal of Automated Reasoning.

[81]  Jason Baumgartner,et al.  Scalable Automated Verification via Expert-System Guided Transformations , 2004, FMCAD.

[82]  Fadi A. Aloul.  Search techniques for SAT-based Boolean optimization , 2006, J. Frankl. Inst..

[83]  Russell Impagliazzo,et al.  On the Exact Complexity of Evaluating Quantified k-CNF , 2010, IPEC.

[84]  Paulo F. Flores,et al.  PMSat: a parallel version of MiniSAT , 2008, J. Satisf. Boolean Model. Comput..

[85]  Kiyoharu Hamaguchi,et al.  Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints , 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[86]  Holger Hermanns,et al.  Logic for Programming, Artificial Intelligence, and Reasoning , 2010, Lecture Notes in Computer Science.

[87]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[88]  R. Wolski,et al.  GridSAT: A Chaff-based Distributed SAT Solver for the Grid , 2003, ACM/IEEE SC 2003 Conference (SC'03).

[89]  O.A. Mohamed,et al.  Integrating SAT with Multiway Decision Graphs for efficient model checking , 2007, 2007 Internatonal Conference on Microelectronics.

[90]  Panagiotis Manolios,et al.  Faster SAT solving with better CNF generation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[91]  P. Bjesse,et al.  DAG-aware circuit compression for formal verification , 2004, ICCAD 2004.

[92]  Martin Fränzle,et al.  Efficient Solving of Large Non-linear Arithmetic Constraint Systems with Complex Boolean Structure , 2007, J. Satisf. Boolean Model. Comput..

[93]  Harry Zhang,et al.  Combining Adaptive Noise and Look-Ahead in Local Search for SAT , 2007, SAT.

[94]  Fangzhen Lin,et al.  ASSAT: computing answer sets of a logic program by SAT solvers , 2002, Artif. Intell..

[95]  Maria Paola Bonacina,et al.  PSATO: a Distributed Propositional Prover and its Application to Quasigroup Problems , 1996, J. Symb. Comput..

[96]  Yuliya Lierler,et al.  SAT-Based Answer Set Programming , 2004, AAAI.

[97]  Adnan Darwiche,et al.  On the Power of Clause-Learning SAT Solvers with Restarts , 2009, CP.

[98]  Wei Wu,et al.  Clause States Based Configuration Checking in Local Search for Satisfiability , 2015, IEEE Transactions on Cybernetics.

[99]  Joao Marques-Silva,et al.  Boolean satisfiability in electronic design automation , 2000, Proceedings 37th Design Automation Conference.

[100]  Kaile Su,et al.  Local Search with Configuration Checking for SAT , 2011, 2011 IEEE 23rd International Conference on Tools with Artificial Intelligence.

[101]  Youssef Hamadi,et al.  A Concurrent Portfolio Approach to SMT Solving , 2009, CAV.

[102]  Marco Bozzano,et al.  The MathSAT 3 System , 2005, CADE.

[103]  Kazunori Ueda,et al.  An interval-based SAT modulo ODE solver for model checking nonlinear hybrid systems , 2011, International Journal on Software Tools for Technology Transfer.

[104]  Ricardo Marqués.  Parallel SAT Solver , 2013 .

[105]  Randal E. Bryant,et al.  Symbolic Boolean manipulation with ordered binary-decision diagrams , 1992, CSUR.

[106]  Adnan Aziz,et al.  Improved SAT-based bounded reachability analysis , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[107]  Michael S. Hsiao,et al.  CNF formula simplification using implication reasoning , 2004, Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940).

[108]  Bart Selman,et al.  Noise Strategies for Improving Local Search , 1994, AAAI.

[109]  Fabio Somenzi,et al.  Strong Conflict Analysis for Propositional Satisfiability , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[110]  Bob Bentley.  Validating a Modern Microprocessor , 2005, CAV.

[111]  Gilles Audemard,et al.  Lazy Clause Exchange Policy for Parallel SAT Solvers , 2014, SAT.

[112]  Sean Forman.  NagSAT; A Randomized Complete, Parallel Solver for 3-SAT , 2002 .

[113]  Hai Zhou,et al.  BDD Based Procedures for a Theory of Equality with Uninterpreted Functions , 2003, Formal Methods Syst. Des..

[114]  Kenneth L. McMillan,et al.  Applying SAT Methods in Unbounded Symbolic Model Checking , 2002, CAV.

[115]  Parosh Aziz Abdulla,et al.  Symbolic Reachability Analysis Based on SAT-Solvers , 2000, TACAS.

[116]  Abdul Sattar,et al.  Local search with edge weighting and configuration checking heuristics for minimum vertex cover , 2011, Artif. Intell..

[117]  Niklas Sörensson.  Effective SAT solving , 2008 .

[118]  Rolf Drechsler,et al.  Speeding up SAT-Based ATPG Using Dynamic Clause Activation , 2009, 2009 Asian Test Symposium.

[119]  Holger H. Hoos,et al.  On the Run-time Behaviour of Stochastic Local Search Algorithms for SAT , 1999, AAAI/IAAI.

[120]  Andrea Formisano,et al.  On multiple learning schemata in conflict driven solvers , 2014, ICTCS.

[121]  Ewing Lusk,et al.  User''s Guide to the p4 Parallel Programming System , 1992 .

[122]  Ofer Shtrichman.  Pruning Techniques for the SAT-Based Bounded Model Checking Problem , 2001 .

[123]  Rolf Drechsler,et al.  On Acceleration of SAT-Based ATPG for Industrial Designs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[124]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[125]  Ju-Sung Kang,et al.  A Study of the Parallelization of Hybrid SAT Solver using CUDA , 2014 .

[126]  Armando Tacchella,et al.  (In)Effectiveness of Look-Ahead Techniques in a Modern SAT Solver , 2003, CP.

[127]  Chi-An Wu,et al.  A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[128]  Niklas Srensson,et al.  An Extensible SAT-solver [ver 1.2] , 2003 .

[129]  Kenneth L. McMillan,et al.  Generalizing DPLL to Richer Logics , 2009, CAV.

[130]  Gil Utard,et al.  A Parallelization Scheme Based on Work Stealing for a Class of SAT Solvers , 2005, Journal of Automated Reasoning.

[131]  Niklas Een,et al.  MiniSat v1.13 - A SAT Solver with Conflict-Clause Minimization , 2005 .

[132]  Alan Mishchenko,et al.  Applying Logic Synthesis for Speeding Up SAT , 2007, SAT.

[133]  Chu Min Li,et al.  Diversification and Determinism in Local Search for Satisfiability , 2005, SAT.

[134]  Tracy Larrabee.  Efficient generation of test patterns using Boolean difference , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[136]  Koen Claessen,et al.  SAT-Based Verification without State Space Traversal , 2000, FMCAD.

[137]  Olivier Roussel,et al.  The International SAT Solver Competitions , 2012, AI Mag..

[138]  Wahid Chrabakh,et al.  GrADSAT: A Parallel SAT Solver for the Grid , 2003 .

[139]  Masahiro Fujita,et al.  Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.

[140]  Karem A. Sakallah,et al.  Automatic abstraction and verification of verilog models , 2004, Proceedings. 41st Design Automation Conference, 2004..