Design of an Area-efficient High-order Leapfrog Delta-Sigma Modulator

This paper describes the design of a 4th-order leapfrog [1] delta-sigma DAC.This topology is less sensitive to coefficient variation.In order to implement the modulator in a most efficient way,here also gives a method of minimizing the word-length of delta-sigma modulator.Further coefficients of the modulator are quantized to power-of-two,so multiplication operations are simplified to bit-shift operations.At the same time the performance is not reduced.Signal to noise ratio(SNR) is the criterion for word-length reduction.