Logic Design and Quantum Mapping of a Novel Four Variable Reversible s2c2 Gate

Reversible Logic has emerged as a topic of massive research owing to its promising heat arresting attribute and being an inherent part of quantum computing. CMOS has already started witnessing physical threshold limits with architectures based on classical irreversible logic functions. Several application specific reversible gates have been proposed in the previous decade. This communication proposes a novel four variable reversible gate capable of implementing a standalone full adder/subtractor. The gate has exhibited better statistics in peer comparisons. The work in this paper illustrates the complete design and construction of the proposed gate along with the quantum realization.

[1]  Keivan Navi,et al.  A Novel Reversible BCD Adder For Nanotechnology Based Systems , 2008 .

[2]  E. Lutz,et al.  Experimental verification of Landauer’s principle linking information and thermodynamics , 2012, Nature.

[3]  Namit Gupta,et al.  Basic Reversible Logic Gates and It's Qca Implementation , 2014 .

[4]  Kamalika Datta,et al.  A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines , 2015, IEEE Transactions on Computers.

[5]  H R Bhagyalakshmi,et al.  Design of a Multifunction BVMF Reversible Logic Gate and its Applications , 2011 .

[6]  K. Poulose Jacob,et al.  Design of compact reversible decimal adder using RPS gates , 2012, 2012 World Congress on Information and Communication Technologies.

[7]  Parag K. Lala,et al.  Reversible-logic design with online testability , 2006, IEEE Transactions on Instrumentation and Measurement.

[8]  Gerhard W. Dueck,et al.  IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION ( VLSI ) SYSTEMS , VOL . ? ? ? , NO . ? ? ? , ? ? ? , 2003 .

[9]  Keivan Navi,et al.  A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems , 2007 .

[10]  Atal Chaudhuri,et al.  A novel reversible two's complement gate (TCG) and its quantum mapping , 2017, 2017 Devices for Integrated Circuit (DevIC).

[11]  Pérès,et al.  Reversible logic and quantum computers. , 1985, Physical review. A, General physics.

[12]  James A. Hutchby,et al.  Limits to binary logic switch scaling - a gedanken model , 2003, Proc. IEEE.

[13]  Muhammad Mahbubur Rahman,et al.  Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders , 2009, 2009 International Conference on Advances in Computational Tools for Engineering Applications.

[14]  Atal Chaudhuri,et al.  Realization of a Novel Reversible SCG Gate and its Application for Designing Parallel Adder/Subtractor and Match Logic , 2011 .

[15]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[16]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[17]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[18]  Himanshu Thapliyal,et al.  Novel Reversible `TSG' Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU , 2005, 2005 5th International Conference on Information Communications & Signal Processing.

[19]  R. Feynman Simulating physics with computers , 1999 .

[20]  Gerhard W. Dueck,et al.  A transformation based algorithm for reversible logic synthesis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[21]  Michael P. Frank,et al.  Introduction to reversible computing: motivation, progress, and challenges , 2005, CF '05.

[22]  Vandana Shukla,et al.  Application of CSMT gate for efficient reversible realization of binary to gray code converter circuit , 2015, 2015 IEEE UP Section Conference on Electrical Computer and Electronics (UPCON).

[23]  M. Arun,et al.  Reversible Arithmetic Logic Gate (ALG) for Quantum Computation , 2013 .

[24]  Atal Chaudhuri,et al.  Comprehensive quantum analysis of existing four variable reversible gates , 2017, 2017 Devices for Integrated Circuit (DevIC).

[25]  S. P. Maity,et al.  Implementation of HNG using MZI , 2012, 2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12).

[26]  Ashis Kumer Biswas,et al.  Efficient approaches for designing reversible Binary Coded Decimal adders , 2008, Microelectron. J..