论文信息 - Novel tri-state latch using single-peak negative differential resistance devices

Novel tri-state latch using single-peak negative differential resistance devices

We propose a novel tri-state latch based on single-peak MOS-NDR. By shifting peak voltage over half of the supply voltage, tri-state memory can be implemented. The fully suppressed valley current of MOS-NDR guarantees the supply voltage design margin in tri-state logic and memory.

Kyung Rok Kim | Sunhae Shin

[1] H. T. Mouftah,et al. Depletion/enhancement CMOS for a lower power family of three-valued logic circuits , 1985 .

[2] Hung Chang Lin,et al. Multivalued SRAM cell using resonant tunneling diodes , 1992 .

[3] Maria J. Avedillo,et al. Efficient realisation of MOS-NDR threshold logic gates , 2009 .