High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters

Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work

[1]  S. Rajapandian,et al.  High-tension power delivery: operating 0.18 /spl mu/m CMOS digital logic at 5.4V , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[2]  Vivek De,et al.  Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[3]  A. Waizman,et al.  Resonant free power network design using extended adaptive voltage positioning (EAVP) methodology , 2001 .

[4]  S. Rajapandian,et al.  A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[5]  Seth R. Sanders,et al.  Converter IC for Cellular Phone Applications , 2004 .

[6]  T. Karnik,et al.  Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.

[7]  F.C. Lee,et al.  1-MHz self-driven ZVS full-bridge converter for 48-V power pod and DC/DC brick , 2005, IEEE Transactions on Power Electronics.

[8]  S. Narendra,et al.  A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package , 2005, IEEE Journal of Solid-State Circuits.

[9]  Jinwen Xiao,et al.  A 4/spl mu/A-quiescent-current dual-mode buck converter IC for cellular phone applications , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[10]  Jaeha Kim,et al.  An efficient digital sliding controller for adaptive power supply regulation , 2001, VLSIC 2001.

[11]  Vivek De,et al.  Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[12]  A.V. Peterchev,et al.  A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications , 2004, IEEE Journal of Solid-State Circuits.

[13]  R. Redl,et al.  Optimizing the load transient response of the buck converter , 1998, APEC '98 Thirteenth Annual Applied Power Electronics Conference and Exposition.