High Speed QPP Generator with Optimized Parallel Architecture for 4G LTE-A System

Abstract In 4G long term evolution advanced (LTE-A), the contention-free quadratic permutation polynomial (QPP) internal interleaver is selected for parallel turbo decoding. However, the specific hardware interleaver is still complicated and low-speed, not refined for LTE-A. Based on this situation, the goal of the study is to present an optimized implementation of highly parallelized QPP generator for higher processing speed and smaller area. To achieve that goal, the pipeline technique and recursion algorithm will be applied. The article at first analyzes the QPP formula and introduces a parallel interleaving algorithm which calculates memory access and sub-block indexes. Then an efficient hardware interleaver is proposed including three implementation points. Finally, the performance analysis is provided to evaluate the proposed scheme and the results show that the proposed method has a good exploration to other QPP generators, which costs fewer hardware slices on a Xilinx Virtex6 field programmable gate array (FPGA) reaching 284 MHz maximum clock frequency. Furthermore, the proposed 32 parallel QPP generator reaches 500 MHz on 65nm COMS with an area of 0.012 mm, which can meet the requirement of a Gbps turbo decoder for 4G LTE-A standard.