Abstracting RTL Designs to the Term Level
暂无分享,去创建一个
[1] Daniel Kroening,et al. Word level predicate abstraction and refinement for verifying RTL Verilog , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[2] Sanjit A. Seshia,et al. Modeling and Verifying Systems Using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions , 2002, CAV.
[3] Z. Hanna,et al. A Lazy and Layered SMT ( B V ) Solver for Hard Industrial Verification Problems ⋆ , 2007 .
[4] Li-Shiuan Peh,et al. Flow control and micro-architectural mechanisms for extending the performance of interconnection networks , 2001 .
[5] David L. Dill,et al. A Decision Procedure for Bit-Vectors and Arrays , 2007, CAV.
[6] Joël Ouaknine,et al. Deciding Bit-Vector Arithmetic with Abstraction , 2007, TACAS.
[7] David L. Dill,et al. Automatic verification of Pipelined Microprocessor Control , 1994, CAV.
[8] Jeffrey S. Foster,et al. Type qualifiers: lightweight specifications to improve software quality , 2002 .
[9] Panagiotis Manolios,et al. Refinement maps for efficient verification of processor models , 2005, Design, Automation and Test in Europe.
[10] Karem A. Sakallah,et al. Automatic abstraction and verification of verilog models , 2004, Proceedings. 41st Design Automation Conference, 2004..
[11] Shuvendu K. Lahiri,et al. Deductive Verification of Advanced Out-of-Order Microprocessors , 2003, CAV.
[12] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[13] Stephan Merz,et al. Model Checking , 2000 .
[14] Randal E. Bryant,et al. Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic , 1999, TOCL.
[15] Peer Johannsen,et al. Speeding up hardware verification by automated data path scaling , 2006 .
[16] Karem A. Sakallah,et al. Refinement strategies for verification methods based on datapath abstraction , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[17] Daniel Kroening,et al. Cogent: Accurate Theorem Proving for Program Verification , 2005, CAV.
[18] Hassen Saïdi,et al. Construction of Abstract State Graphs with PVS , 1997, CAV.
[19] Karem A. Sakallah,et al. CEGAR-Based Formal Hardware Verification : A Case Study , 2005 .
[20] E. Clarke,et al. Symbolic model checking using SAT procedures instead of BDDs , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).
[21] Per Bjesse. A Practical Approach to Word Level Model Checking of Industrial Netlists , 2008, CAV.
[22] Warren A. Hunt,et al. Microprocessor design verification , 1989, Journal of Automated Reasoning.