VHDL Semantics for Behavioral Test Generation

Abstract In this paper, we discuss how the VHDL semantics which represent the concepts of event-driven simulation and bus resolution function affect the test generation algorithm, and present methods of generating realistic tests without being affected by the VHDL semantics. A formal representation of the VHDL process statement is described and the concept of event-driven simulation and its impact on test generation are discussed using the formal representation. The new test generation method generates realistic tests by ignoring the sensitivity list of a process statement and identifying the type of the behavior described by the statements inside the process statement (two types of behavior - synchronous and asynchronous, are defined.). A systematic way of converting a VHDL model to one suitable for checking the validity of the generated tests is presented. A method of further compacting the generated tests is also presented. Finally, an approach to generating tests in the presence of different types of bus resolution functions is discussed.

[1]  Stephen Y. H. Su,et al.  The S-Algorithm: A Promising Solution for Systematic Functional Test Generation , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  James R. Armstrong,et al.  A Heuristic Chip-Level Test Generation Algorithm , 1986, DAC 1986.

[3]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[4]  Sumit Ghosh,et al.  On behavior fault modeling for combinational digital designs , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[5]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[6]  Ramin Khorram.  Functional Test Pattern Generation for Integrated Circuits , 1984, ITC.

[7]  J.R. Armstrong.  Chip-level modeling with HDLs , 1988, IEEE Design & Test of Computers.

[8]  Premachandran R. Menon,et al.  Test Generation Algorithms for Computer Hardware Description Languages , 1982, IEEE Transactions on Computers.

[9]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[10]  John Grason,et al.  RTG: Automatic Register Level Test Generator , 1985, DAC 1985.

[11]  V.D. Agrawal,et al.  Designing circuits with partial scan , 1988, IEEE Design & Test of Computers.