Clock refinement in imperative synchronous languages

AbstractThe synchronous model of computation divides the program execution into a sequence of logical steps. On the one hand, this view simplifies many analyses and synthesis procedures, but on the other hand, it imposes restrictions on the modeling and optimization of systems. In this article, we introduce refined clocks in imperative synchronous languages to overcome these restrictions while still preserving important properties of the basic model. We first present the idea in detail and motivate various design decisions with respect to the language extension. Then, we sketch all the adaptations needed in the design flow to support refined clocks.

[1]  K. Schneider,et al.  A new method for compiling schizophrenic synchronous programs , 2001, CASES '01.

[2]  Andreas Krall,et al.  Software and Compilers for Embedded Systems , 2003, Lecture Notes in Computer Science.

[3]  Ephraim Feig,et al.  Fast algorithms for the discrete cosine transform , 1992, IEEE Trans. Signal Process..

[4]  David L. Dill,et al.  The Murphi Verification System , 1996, CAV.

[5]  Pascal Raymond,et al.  The synchronous data flow programming language LUSTRE , 1991, Proc. IEEE.

[6]  Robert de Simone,et al.  Curing schizophrenia by program rewriting in Esterel , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..

[7]  Sandeep K. Shukla,et al.  Integrating system descriptions by clocked guarded actions , 2011, FDL 2011 Proceedings.

[8]  Gérard Berry,et al.  The foundations of Esterel , 2000, Proof, Language, and Interaction.

[9]  Sandeep K. Shukla,et al.  EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications , 2009, 2009 Forum on Specification & Design Languages (FDL).

[10]  Jordi Cortadella,et al.  Synthesis of synchronous elastic architectures , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[11]  Klaus Schneider,et al.  Embedding imperative synchronous languages in interactive theorem provers , 2001, Proceedings Second International Conference on Application of Concurrency to System Design.

[12]  Frances E. Allen,et al.  Control-flow analysis , 2022 .

[13]  Ellen Sentovich,et al.  Multiclock Esterel , 2001, CHARME.

[14]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Gérard Berry,et al.  The constructive semantics of pure esterel , 1996 .

[16]  Nicolas Halbwachs,et al.  LUSTRE: A declarative language for programming synchronous systems* , 1987 .

[17]  Klaus Schneider,et al.  Exact high level WCET analysis of synchronous programs by symbolic state space exploration , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[18]  Correct Hardware Design and Verification Methods , 1993, Lecture Notes in Computer Science.

[19]  R. K. Shyamasundar,et al.  Modeling Distributed Embedded Systems in Multiclock ESTEREL , 2000, FORTE.

[20]  Klaus Schneider,et al.  A Formal Semantics of Clock Refinement in Imperative Synchronous Languages , 2010, 2010 10th International Conference on Application of Concurrency to System Design.

[21]  Jean-Christophe Le Lann,et al.  POLYCHRONY for System Design , 2003, J. Circuits Syst. Comput..

[22]  D. Huffman A Method for the Construction of Minimum-Redundancy Codes , 1952 .

[23]  Tobias Schüle,et al.  A Verified Compiler for Synchronous Programs with Local Declarations , 2006, SLAP@ETAPS.

[24]  Klaus Schneider,et al.  Desynchronizing Synchronous Programs by Modes , 2009, 2009 Ninth International Conference on Application of Concurrency to System Design.

[25]  E.A. Lee,et al.  Synchronous data flow , 1987, Proceedings of the IEEE.

[26]  corporateName,et al.  Design Automation Conference (DAC) , 2011 .

[27]  Klaus Schneider,et al.  Multithreaded Code from Synchronous Programs: Generating Software Pipelines for OpenMP , 2010, MBMV.

[28]  Sanjit A. Seshia,et al.  A Translation of Statecharts to Esterel , 1999, World Congress on Formal Methods.

[29]  Arvind Bluespec: A language for hardware design, simulation, synthesis and verification Invited Talk , 2003, MEMOCODE.

[30]  Reinhard von Hanxleden,et al.  Synthesizing safe state machines from Esterel , 2006, LCTES '06.

[31]  Klaus Schneider,et al.  Separate compilation for synchronous programs , 2009, SCOPES.

[32]  Leslie Lamport,et al.  The temporal logic of actions , 1994, TOPL.

[33]  Sharad Malik,et al.  Performance analysis of real-time embedded software , 1997 .

[34]  Frank Mueller,et al.  Languages, Compilers, and Tools for Embedded Systems , 1998, Lecture Notes in Computer Science.

[35]  Abdoulaye Gamatié Designing Embedded Systems with the SIGNAL Programming Language - Synchronous, Reactive Specification , 2010 .

[36]  Thierry Gautier,et al.  Programming real-time applications with SIGNAL , 1991, Proc. IEEE.

[37]  Sandeep K. Shukla,et al.  Constructive polychronous systems , 2013, Sci. Comput. Program..

[38]  Tobias Schüle,et al.  Maximal causality analysis , 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).

[39]  Taisook Han,et al.  Refining schizophrenia via graph reachability in Esterel , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.

[40]  Alain Girault,et al.  Clock-Driven Automatic Distribution of Lustre Programs , 2003, EMSOFT.

[41]  Stephen A. Edwards,et al.  The Synchronous Languages Twelve Years Later , 1997 .

[42]  David Harel,et al.  Statecharts: A Visual Formalism for Complex Systems , 1987, Sci. Comput. Program..

[43]  Amnon Naamad,et al.  The STATEMATE semantics of statecharts , 1996, TSEM.

[44]  Gordon D. Plotkin,et al.  A structural approach to operational semantics , 2004, J. Log. Algebraic Methods Program..

[45]  Sandeep K. Shukla,et al.  Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications , 2007, Power-aware Computing Systems.

[46]  R. K. Shyamasundar,et al.  Multiclock Esterel: a reactive framework for asynchronous design , 2000, Proceedings 14th International Parallel and Distributed Processing Symposium. IPDPS 2000.

[47]  G. Plotkin,et al.  Proof, language, and interaction: essays in honour of Robin Milner , 2000 .

[48]  Joe D. Warren,et al.  The program dependence graph and its use in optimization , 1987, TOPL.

[49]  Karl J. Ottenstein,et al.  The program dependence graph in a software development environment , 1984 .

[50]  Klaus Schneider,et al.  Translating Synchronous Systems to Data-Flow Process Networks , 2011, 2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies.

[51]  Sharad Malik Analysis of cyclic combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[52]  Peter D. Mosses Formal Semantics of Programming Languages: - An Overview - , 2006, Electron. Notes Theor. Comput. Sci..

[53]  Christiane Rousseau,et al.  Image Compression The JPEG Standard , 2008 .

[54]  Stephen A. Edwards,et al.  SHIM: A Language for Hardware/Software Integration , 2004, SYNCHRON.

[55]  Stephen A. Edwards,et al.  The synchronous languages 12 years later , 2003, Proc. IEEE.

[56]  Gérard Berry,et al.  The ESTEREL Synchronous Programming Language and its Mathematical Semantics , 1984, Seminar on Concurrency.

[57]  Jordi Cortadella,et al.  Synchronous Elastic Networks , 2006, 2006 Formal Methods in Computer Aided Design.

[58]  Stephen A. Edwards,et al.  SHIM: a deterministic model for heterogeneous embedded systems , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[59]  Edward A. Lee,et al.  A framework for comparing models of computation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[60]  Edward A. Lee,et al.  Hierarchical finite state machines with multiple concurrency models , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[61]  Klaus Schneider,et al.  From Synchronous Guarded Actions to SystemC , 2010, MBMV.

[62]  Frédéric Boussinot,et al.  SugarCubes Implementation of Causality , 1998 .

[63]  Amir Pnueli,et al.  On the Development of Reactive Systems , 1989, Logics and Models of Concurrent Systems.

[64]  Klaus Schneider,et al.  Causality analysis of synchronous programs with refined clocks , 2011, 2011 IEEE International High Level Design Validation and Test Workshop.

[65]  Stephen A. Edwards Compiling Esterel into sequential code , 2000, DAC.

[66]  Gilles Kahn,et al.  The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.

[67]  Tobias Schüle,et al.  Abstraction of assembler programs for symbolic worst case execution time analysis , 2004, Proceedings. 41st Design Automation Conference, 2004..

[68]  Edward A. Lee The problem with threads , 2006, Computer.

[69]  Giovanni Motta,et al.  Handbook of Data Compression , 2009 .

[70]  Andreas Veneris,et al.  Formal methods in computer-aided design , 2012, FMCAD 2012.

[71]  G.S. Moschytz,et al.  Practical fast 1-D DCT algorithms with 11 multiplications , 1989, International Conference on Acoustics, Speech, and Signal Processing,.

[72]  Kenneth J. Turner,et al.  Correct Hardware Design and Verification Methods , 2001, Lecture Notes in Computer Science.

[73]  T. Agerwala,et al.  Putting Petri nets to work , 1989 .

[74]  Robert de Simone,et al.  The Synchronous Hypothesis and Synchronous Languages , 2005, Embedded Systems Handbook.

[75]  Nicolas Halbwachs,et al.  A synchronous language at work: the story of Lustre , 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

[76]  Klaus Schneider,et al.  Compilation of imperative synchronous programs with refined clocks , 2010, Eighth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010).

[77]  Thomas R. Shiple,et al.  Constructive analysis of cyclic circuits , 1996, Proceedings ED&TC European Design and Test Conference.

[78]  Stephen A. Edwards,et al.  Making cyclic circuits acyclic , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[79]  Klaus Schneider,et al.  Multithreaded code from synchronous programs: Extracting independent threads for OpenMP , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[80]  Nicolas Halbwachs,et al.  Generating Efficient Code From Data-Flow Programs , 1991, PLILP.

[81]  Michael Mendler,et al.  WCRT algebra and interfaces for esterel-style synchronous processing , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[82]  Dhiraj K. Pradhan,et al.  Design Automation and Test in Europe (DATE) , 2014 .

[83]  R. K. Shyamasundar,et al.  Modelling VHDL in multiclock ESTEREL , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[84]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[85]  Benoît Caillaud,et al.  Concurrency in synchronous systems , 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

[86]  Edward A. Lee,et al.  Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing , 1989, IEEE Transactions on Computers.

[87]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[88]  Klaus Schneider,et al.  Performing causality analysis by bounded model checking , 2008, 2008 8th International Conference on Application of Concurrency to System Design.

[89]  Sandeep K. Shukla,et al.  Faster Software Synthesis Using Actor Elimination Techniques for Polychronous Formalism , 2010, 2010 10th International Conference on Application of Concurrency to System Design.

[90]  Albert Benveniste,et al.  Concurrency in Synchronous Systems , 2006, Formal Methods Syst. Des..

[91]  P. Guernic,et al.  Arborescent canonical form of boolean expressions , 1994 .

[92]  Sandeep K. Shukla,et al.  Algorithms for low power hardware synthesis from Concurrent Action Oriented Specifications (CAOS) , 2007, Int. J. Embed. Syst..

[93]  Klaus Schneider,et al.  The Synchronous Programming Language Quartz , 2009 .

[94]  Carl-Johan H. Seger,et al.  Asynchronous Circuits , 1995, Monographs in Computer Science.

[95]  Franz J. Rammig Distributed and Parallel Embedded Systems , 1999 .

[96]  Jens Palsberg,et al.  Nonintrusive precision instrumentation of microcontroller software , 2005, LCTES '05.

[97]  Sandeep K. Shukla,et al.  An alternative polychronous model and synthesis methodology for model-driven embedded software , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[98]  C. A. Petri Introduction to General Net Theory , 1979, Advanced Course: Net Theory and Applications.

[99]  Samarjit Chakraborty,et al.  Timing analysis of esterel programs on general-purpose multiprocessors , 2010, Design Automation Conference.

[100]  K. Mani Chandy Parallel program design , 1989 .

[101]  Premachandran R. Menon,et al.  Redundancy identification and removal in combinational circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[102]  Gérard Berry,et al.  Esterel on hardware , 1992, Philosophical Transactions of the Royal Society of London. Series A: Physical and Engineering Sciences.

[103]  Nicolas Halbwachs,et al.  Implementing Reactive Programs on Circuits: A Hardware Implementation of LUSTRE , 1991, REX Workshop.

[104]  Paul Le Guernic,et al.  SIGNAL: A declarative language for synchronous programming of real-time systems , 1987, FPCA.

[105]  Nicolas Halbwachs,et al.  Synchronous Programming of Reactive Systems , 1992, CAV.

[106]  Gérard Berry,et al.  The Esterel Synchronous Programming Language: Design, Semantics, Implementation , 1992, Sci. Comput. Program..

[107]  Jean-Pierre Jouannaud,et al.  Functional Programming Languages and Computer Architecture , 1985, Lecture Notes in Computer Science.

[108]  Gérard Berry,et al.  A hardware implementation of pure ESTEREL , 1992 .

[109]  A. Sangiovanni-Vincentelli,et al.  Formal analysis of synchronous circuits , 1996 .

[110]  Klaus Schneider,et al.  Out-Of-order execution of synchronous data-flow networks , 2012, 2012 International Conference on Embedded Computer Systems (SAMOS).

[111]  Klaus Schneider,et al.  Schizophrenia and causality in the context of refined clocks , 2011, FDL 2011 Proceedings.

[112]  Nicolas Halbwachs,et al.  On the Symbolic Analysis of Combinational Loops in Circuits and Synchronous Programs , 1995 .

[113]  Benoît Caillaud,et al.  Correct-by-construction asynchronous implementation of modular synchronous specifications , 2005, Fifth International Conference on Application of Concurrency to System Design (ACSD'05).

[114]  Albert Benveniste,et al.  The synchronous approach to reactive and real-time systems , 1991 .

[115]  Tobias Schüle,et al.  Causality analysis of synchronous programs with delayed actions , 2004, CASES '04.

[116]  Stephen A. Edwards,et al.  An Esterel compiler for large control-dominated systems , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[117]  Christos G. Cassandras,et al.  Introduction to Discrete Event Systems , 1999, The Kluwer International Series on Discrete Event Dynamic Systems.

[118]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1991, CACM.

[119]  Eric Hamilton JPEG File Interchange Format , 2004 .

[120]  Sandeep K. Shukla,et al.  Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions , 2014, Des. Autom. Embed. Syst..

[121]  Klaus Schneider,et al.  Static data-flow analysis of synchronous programs , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.

[122]  Sandeep K. Shukla,et al.  Embedding Polychrony into Synchrony , 2013, IEEE Transactions on Software Engineering.

[123]  James C. Hoe,et al.  Hardware Synthesis from Term Rewriting Systems , 1999, VLSI.

[124]  Mirabelle Nebut,et al.  An Overview of the Signal Clock Calculus , 2004, SLAP.

[125]  Stephen A. Edwards,et al.  Compiling Concurrent Languages for Sequential Processors , 2001 .

[126]  Marian Boldt,et al.  Worst Case Reaction Time Analysis of Concurrent Reactive Programs , 2008, Electron. Notes Theor. Comput. Sci..

[127]  Sandeep K. Shukla,et al.  Synthesis of Embedded Software - Frameworks and Methodologies for Correctness by Construction , 2010, Synthesis of Embedded Software.

[128]  Klaus Schneider,et al.  Separate Translation of Synchronous Programs to Guarded Actions , 2011 .

[129]  Michael Harder,et al.  An Esterel processor with full preemption support and its worst case reaction time analysis , 2005, CASES '05.