Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code

Deep submicrometer devices are expected to be increasingly sensitive to physical faults. For this reason, fault-tolerance mechanisms are more and more required in VLSI circuits. So, validating their dependability is a prior concern in the design process. Fault injection techniques based on the use of hardware description languages offer important advantages with regard to other techniques. First, as this type of techniques can be applied during the design phase of the system, they permit reducing the time-to-market. Second, they present high controllability and reachability. Among the different techniques, those based on the use of saboteurs and mutants are especially attractive due to their high fault modeling capability. However, implementing automatically these techniques in a fault injection tool is difficult. Especially complex are the insertion of saboteurs and the generation of mutants. In this paper, we present new proposals to implement saboteurs and mutants for models in VHDL which are easy-to-automate, and whose philosophy can be generalized to other hardware description languages.

[1]  Javier Uceda,et al.  A fault model for VHDL descriptions at the register transfer level , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[2]  Joaquin Gracia,et al.  VHDL Simulation-Based Fault Injection Techniques , 2003 .

[3]  Johan Karlsson,et al.  Fault injection into VHDL models: the MEFISTO tool , 1994 .

[4]  Weiwei Mao,et al.  Improving gate level fault coverage by RTL fault grading , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[5]  Marco Ottavi,et al.  Bit flip injection in processor-based architectures: a case study , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[6]  Alfredo Benso,et al.  Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[7]  Pedro J. Gil,et al.  Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system , 2003, Microelectron. J..

[8]  Régis Leveugle,et al.  A new approach for early dependability evaluation based on formal property checking and controlled mutations , 2005, 11th IEEE International On-Line Testing Symposium.

[9]  Cristian Constantinescu,et al.  Impact of deep submicron technology on dependability of VLSI circuits , 2002, Proceedings International Conference on Dependable Systems and Networks.

[10]  Sumit Ghosh,et al.  On behavior fault modeling for digital designs , 1991, J. Electron. Test..

[11]  Barry W. Johnson,et al.  A Fault Injection Technique for VHDL Behavioral-Level Models , 1996, IEEE Des. Test Comput..

[12]  Yves Crouzet,et al.  MEFISTO-L: a VHDL-based fault injection tool for the experimental assessment of fault tolerance , 1998, Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224).

[13]  Pedro J. Gil,et al.  Impact of Faults in Combinational Logic of Commercial Microcontrollers , 2005, EDCC.

[14]  Vishwani D. Agrawal,et al.  A test evaluation technique for VLSI circuits using register-transfer level fault modeling , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Pedro J. Gil,et al.  A prototype of a VHDL-based fault injection tool: description and application , 2002, J. Syst. Archit..

[16]  Pedro J. Gil,et al.  A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[17]  Volkmar Sieh,et al.  VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions , 1997, Proceedings of IEEE 27th International Symposium on Fault Tolerant Computing.

[18]  Seyed Ghassem Miremadi,et al.  Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs , 2007, Microelectron. Reliab..

[19]  Jean Arlat,et al.  Fault Injection for Dependability Validation: A Methodology and Some Applications , 1990, IEEE Trans. Software Eng..

[20]  Pablo Sanchez,et al.  System level fault simulation , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[21]  Cristian Constantinescu.  Neutron SER characterization of microprocessors , 2005, 2005 International Conference on Dependable Systems and Networks (DSN'05).

[22]  Pedro J. Gil,et al.  Improvement of fault injection techniques based on VHDL code modification , 2005, Tenth IEEE International High-Level Design Validation and Test Workshop, 2005..

[23]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.