Formal Analysis of Memory Contention in a Multiprocessor System

Multi-core processors along with multi-module memories are extensively being used in high performance computers these days. One of the main performance evaluation metrics in such configurations is the memory contention problem and its effect on the overall memory access time. Usually, this problem is analyzed using simulation or numerical methods. However, these methods either cannot guarantee accurate analysis or are not scalable due to the unacceptable computation times. As an alternative approach, this paper uses theorem proving to analyze the memory contention problem of a multiprocessor system. For this purpose, the paper presents the higher-order-logic formalization of the expectation of a discrete random variable and Discrete-time Markov Reward Models. These foundations are then utilized to analyze the memory contention problem of a multi-processor system configuration with two processors and two memory modules using the HOL theorem prover.