Research on Evolution Mechanism in Different-Structure Module Redundancy Fault-Tolerant System

With the dramatic increase of circuit scale and the harsh environment, the reliability of the system has become the great hidden danger. Triple different-structure modular redundant system based on evolution mechanism shows good fault tolerant ability. How to enhance the efficiency and diversity of the evolution generation module has become the key issue which can ensure the system fault tolerant. This article puts forward two-stage mutation evolution strategy (TMES) and interactive two-stage mutation evolution strategy (ITMES) based on improving virtual reconfigurable architecture platform to evolve combination logical circuit on the fault-tolerant system with different-structure redundancy module. The efficiency of the proposed methodology is tested with the evolutions of a 2-bit multipliers, and a 3-bit multipliers, and a 3-bit full adders. The obtained results demonstrate the effectiveness of the scheme on generation circuit diversity and evolution efficiency.

[1]  Li Yuan-xiang Optimization algorithm for complicated circuit based on GEP , 2008 .

[2]  M. Caffrey,et al.  Evaluating TMR Techniques in the Presence of Single Event Upsets , 2003 .

[3]  Gunnar Tufte Discovery and Investigation of Inherent Scalability in Developmental Genomes , 2008, ICES.

[4]  Julian Francis Miller,et al.  Scalability problems of digital circuit evolution evolvability and efficient designs , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[5]  Xu Gui-li Research on Technology of Different-structure System Based on Evolvable Hardware , 2009 .

[6]  J. Sitte,et al.  Chapter 11 Issues in the Scalability of Gate-Level Morphogenetic Evolvable Hardware , 2005, Recent Advances in Artificial Life.

[7]  Jin Wang,et al.  Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware , 2008, IET Comput. Digit. Tech..

[8]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[9]  Lukás Sekanina Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware , 2003, ICES.

[10]  Yao Rui Research on redundancy and tolerance of system with different structures , 2007 .

[11]  Jin Wang,et al.  Virtual reconfigurable architecture for evolving combinational logic circuits , 2014 .

[12]  Peter J. Bentley,et al.  Towards development in evolvable hardware , 2002, Proceedings 2002 NASA/DoD Conference on Evolvable Hardware.

[13]  Chen Ze-wang Design and Experiments of Enhanced Fault-Tolerant Triple-Module Redundancy Systems Capable of Online Self-Repairing , 2010 .

[14]  Kenji Toda,et al.  Real-world applications of analog and digital evolvable hardware , 1999, IEEE Trans. Evol. Comput..

[15]  Julian Francis Miller,et al.  Redundancy and computational efficiency in Cartesian genetic programming , 2006, IEEE Transactions on Evolutionary Computation.

[16]  Kyrre Glette,et al.  A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device , 2005, ICES.

[17]  M. Wirthlin,et al.  Fine-Grain SEU Mitigation for FPGAs Using Partial TMR , 2008, IEEE Transactions on Nuclear Science.

[18]  Julian Francis Miller,et al.  The Advantages of Landscape Neutrality in Digital Circuit Evolution , 2000, ICES.

[19]  Mihai Oltean,et al.  Evolving digital circuits using multi expression programming , 2004, Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004..