Statistical skew modeling for general clock distribution networks in presence of process variations

Clock skew modeling is important in the performance evaluation and prediction of clock distribution networks. This paper addresses the problem of statistical skew modeling for general clock distribution networks in the presence of process variations. The only available statistical skew model is not suitable for modeling the clock skews of general clock distribution networks in which clock paths are not identical. The old model is also too conservative for estimating the clock skew of a well-balanced clock network that has identical but strongly correlated clock paths (for instance, a well-balanced H-tree). In order to provide a more accurate and more general statistical skew model for general clock distributions, we propose a new approach to estimating the mean values and variances of both clock skews and the maximal clock delay of general clock distribution networks. Based on the new approach, a closed-form model is also obtained for well-balanced H-tree clock distribution networks. The paths delay correlation caused by the overlapped parts of path lengths is considered in the new approach, so the mean values and the variances of both clock skews and the maximal clock delay are accurately estimated for general clock distribution networks. This enables an accurate estimate of yields of both clock skew and maximal clock delay to be made for a general clock distribution network.

[1]  K. R. Lakshmikumar,et al.  Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .

[2]  I. P. Jalowiecki,et al.  The influence of process parameter variations on the signal distribution behaviour of wafer scale integration devices , 1995 .

[3]  Kenneth Steiglitz,et al.  An Upper Bound on Expected Clock Skew in Synchronous Systems , 1990, IEEE Trans. Computers.

[4]  W. Sansen,et al.  Mismatch Characterization of Submicron MOS Transistors , 1997 .

[5]  Trevor York,et al.  Book Review: Principles of CMOS VLSI Design: A Systems Perspective , 1986 .

[6]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[7]  Xiaohong Jiang,et al.  Optimization of wafer scale H-tree clock distribution network based on a new statistical skew model , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[8]  M. Shoji,et al.  Elimination of process-dependent clock skew in CMOS VLSI , 1986 .

[9]  Doris Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, ISLPED '96.

[10]  I. Miller.  Probability, Random Variables, and Stochastic Processes , 1966 .

[11]  Athanasios Papoulis,et al.  Probability, Random Variables and Stochastic Processes , 1965 .

[12]  Yvon Savaria,et al.  Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[13]  H. T. Kung,et al.  Synchronizing Large VLSI Processor Arrays , 1983, IEEE Transactions on Computers.

[14]  H. Fair,et al.  Clocking design and analysis for a 600 MHz Alpha microprocessor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[15]  A. Kahng,et al.  On optimal interconnections for VLSI , 1994 .

[16]  Donatella Sciuto,et al.  Clock skew reduction in ASIC logic design: a methodology for clock tree management , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Steven D. Kugelmass,et al.  A probabilistic model for clock skew , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[18]  D. Schmitt-Landsiedel,et al.  The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[19]  Christer Svensson,et al.  Performance of Synchronous and Asynchronous Schemes for VLSI Systems , 1992, IEEE Trans. Computers.

[20]  D. C. Keezer,et al.  A comparative study of clock distribution approaches for WSI , 1993, 1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration.

[21]  Eby G. Friedman.  Clock distribution networks in VLSI circuits and systems , 1995 .

[22]  S. Horiguchi,et al.  Distribution analysis of clock skew and clock delay for general clock dis , 2000 .

[23]  Susumu Horiguchi,et al.  A recursive approach to estimating clock skew yield and clock delay yield for general clock distribution networks , 2000 .