인지 무선 통신 시스템을 위한 다중 상관기 출력값 결합 기반 UWB 신호 검파 기법

The purpose of this diploma thesis is the design and implementation of a dual loop frequency synthesizer, operating at frequencies ranging from 3 to 6 GHz, for wireless network applications, using UWB and HiperLAN2 standards. The frequency synthesizer’s design was based on dual loop synthesizer architecture and the use of modular components. The designed frequency synthesizer is able to function in 2 modes, by either producing signals in the frequency range of 3168 MHz 6336 MHz with 528 MHz resolution, or signals in the frequency range of 4800 MHz 5000 MHz with 10 MHz resolution. Although the dual loop architecture has long been replaced by the fractional-N architecture due to increased cost and power consumption, it is more suitable in wireless network applications demanding high precision in frequency synthesis and low phase noise. The integer-N architecture fails to satisfy these demands, due to the limited loop bandwidth and the large division ratio Ν of the loop’s frequency divider. The dual loop architecture uses two loops in order to alleviate the opposing demands in high frequency synthesis accuracy and low phase noise, which determine the behavior and performance of the frequency synthesizer. The use of modular components aims at better phase noise performance, as well as a more flexible design, thus resulting in a more efficient power dissipation of the spurious components of the reference signal at the synthesizer output.