SCRIPT: a critical path tracing algorithm for synchronous sequential circuits
暂无分享,去创建一个
[1] Sunil Jain,et al. Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.
[2] Balakrishnan Krishnamurthy,et al. A graph compaction approach to fault simulation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[3] Kurt Antreich,et al. Accelerated Fault Simulation and Fault Grading in Combinational Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] Douglas B. Armstrong,et al. A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.
[5] M. Abramovici,et al. SMART And FAST: Test Generation for VLSI Scan-Design Circuits , 1986, IEEE Design & Test of Computers.
[6] P. R. Menon,et al. Critical Path Tracing: An Alternative to Fault Simulation , 1984, IEEE Des. Test.
[7] Thomas W. Williams,et al. A logic design structure for LSI testability , 1977, DAC '77.
[8] Füsun Özgüner,et al. 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits , 1978, IEEE Transactions on Computers.
[9] Premachandran R. Menon,et al. Critical path tracing in sequential circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[10] James B. Angell,et al. Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.
[11] Franc Brglez,et al. A Fast Fault Grader: Analysis and Applications , 1985, International Test Conference.
[12] Sundaram Seshu,et al. On an Improved Diagnosis Program , 1965, IEEE Trans. Electron. Comput..
[13] Wu-Tung Cheng,et al. Differential Fault Simulation - A Fast Method Using Minimal Memory , 1989, 26th ACM/IEEE Design Automation Conference.
[14] Ernst G. Ulrich,et al. Concurrent simulation of nearly identical digital networks , 1974, Computer.
[15] Janusz Rajski,et al. A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[16] Edward J. McCluskey. Iterative Combinational Switching Networksߞ General Design Considerations , 1958, IRE Trans. Electron. Comput..
[17] Vishwani D. Agrawal,et al. A sequential circuit test generation using threshold-value simulation , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.
[18] David T. Wang. Properties of Faults and Criticalities of Values under Tests for Combinational Networks , 1975, IEEE Transactions on Computers.
[19] Wuudiann Ke,et al. A fast fault simulation algorithm for combinational circuits , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[20] J. Paul Roth,et al. Diagnosis of automata failures: a calculus and a method , 1966 .
[21] J. Paul Roth,et al. A Heuristic Algorithm for the Testing of Asynchronous Circuits , 1971, IEEE Transactions on Computers.
[22] Wei-Kang Huang,et al. A new two task algorithm for clock mode fault simulation in sequential circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[23] John A. Waicukauski,et al. A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation , 1985, ITC.