The iWarp communication system supports two widely used interprocessor communication styles: memory communication and systolic communication. A description is given of the rationale, architecture, and implementation for the iWarp communication system. Memory communication is flexible and well suited for general computing, whereas systolic communication is efficient and well suited for speed-critical applications. The iWarp design is made possible by two important innovations in communication: (1) program access to communication and (2) logical channels. The former allows programs to access data as they are transmitted and to redirect portions of messages to different destinations efficiently. The latter increases the connectivity between the processors and guarantees communication bandwidth for classes of messages. These innovations have provided a focus for the iWarp architecture. The result is a communication system that provides a total bandwidth of 320 MBytes/sec and that is integrated on a single VLSI component with a 20 MFLOPS plus 20 MIPS long instruction work computation engine.<<ETX>>