Sample-and-Hold

The sample-and-hold circuit or track-and-hold circuit performs the sampling operation. These circuits have to operate at the highest signal levels and speeds, which makes their design a challenge. The chapter discusses first the specific metrics for these circuits, such as pedestal step, droop time, and hold-mode feedthrough. The different elements, switch, capacitor, and buffer, are discussed. Some architectures and often applied implementation schemes are shown. The trade-off between noise and distortion requires a careful balance to achieve the optimum performance.

[1]  J.R. Naylor.  A complete high-speed voltage output 16-bit monolithic DAC , 1983, IEEE Journal of Solid-State Circuits.

[2]  G. Bouche,et al.  Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance , 2002, Digest. International Electron Devices Meeting,.

[3]  A. Ziel.  Noise in solid state devices and circuits , 1986 .

[4]  C.E. Shannon,et al.  Communication in the Presence of Noise , 1949, Proceedings of the IRE.

[5]  D.K. Su,et al.  A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC , 2005, IEEE Journal of Solid-State Circuits.

[6]  Ieee Std,et al.  IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters , 2011 .

[7]  E.J. van der Zwan,et al.  A 0.2 mW CMOS /spl Sigma//spl Delta/ modulator for speech coding with 80 dB dynamic range , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[8]  Stephen H. Lewis,et al.  A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers , 1997, IEEE J. Solid State Circuits.

[9]  K. Sakui,et al.  A CMOS bandgap reference circuit with sub-1-V operation , 1999 .

[10]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[11]  Scott Gregory Bardsley,et al.  A 100-dB SFDR 80-MSPS 14-bit 0.35-μm BiCMOS pipeline ADC , 2006 .

[12]  Qiuting Huang.  Phase noise to carrier ratio in LC oscillators , 2000 .

[13]  Willy Sansen,et al.  Design techniques for improved capacitor area efficiency in switched-capacitor biquads , 1987 .

[14]  D. Hilbiber.  A new semiconductor voltage standard , 1964 .

[15]  Akira Matsuzawa,et al.  Sub 1 V CMOS bandgap reference design techniques: a survey , 2010 .

[16]  A.H.M. van Roermund,et al.  Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer , 2006, IEEE Journal of Solid-State Circuits.

[17]  P.G.A. Jespers,et al.  A CMOS 13-b cyclic RSD A/D converter , 1992, IEEE Journal of Solid-State Circuits.

[18]  R. Castello,et al.  A 1 V 1.8 MHz CMOS switched-opamp SC filter with rail-to-rail output swing , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[19]  R. J. van de Plassche,et al.  A high-speed 7 bit A/D converter , 1979 .

[20]  W. Sansen,et al.  Mismatch characterization of small size MOS transistors , 1995, Proceedings International Conference on Microelectronic Test Structures.

[21]  Xuemei Xi,et al.  A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[22]  Claudio Nani,et al.  A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[23]  William H. Beyer,et al.  CRC standard mathematical tables , 1976 .

[24]  Bram Nauta.  Analog CMOS Filters for Very High Frequencies , 1992 .

[25]  R. Sallen,et al.  A practical method of designing RC active filters , 1955, IRE Transactions on Circuit Theory.

[26]  Masao Nakaya,et al.  An 80-MHz 8-bit CMOS D/A converter , 1986 .

[27]  Willy Sansen,et al.  Distortion in elementary transistor circuits , 1999 .

[28]  M.F. Snoeij,et al.  Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors , 2007, IEEE Journal of Solid-State Circuits.

[29]  Paul S. Ho,et al.  Electromigration reliability issues in dual-damascene Cu interconnections , 2002, IEEE Trans. Reliab..

[30]  C. E. SHANNON,et al.  A mathematical theory of communication , 1948, MOCO.

[31]  A. Asenov,et al.  Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture , 2007, IEEE Transactions on Electron Devices.

[32]  Franco Maloberti.  Data Converters , 2007 .

[33]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[34]  Willy Sansen,et al.  A CMOS temperature-compensated current reference , 1988 .

[35]  Ali Hajimiri,et al.  Capacity limits and matching properties of integrated capacitors , 2002, IEEE J. Solid State Circuits.

[36]  L. Rabiner,et al.  A computer program for designing optimum FIR linear phase digital filters , 1973 .

[37]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[38]  Jorge Pernillo,et al.  A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[39]  D. Leenaerts,et al.  A 12b 500MS/s DAC with >70dB SFDR up to 120MHz in 0.18μm CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[40]  A. Keramat,et al.  A capacitor mismatch and gain insensitive 1.5-bit/stage pipelined A/D converter , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[41]  Haruo Kobayashi,et al.  Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .

[42]  K. Nguyen,et al.  A 113 dB SNR oversampling DAC with segmented noise-shaped scrambling , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[43]  P.R. Gray,et al.  A precision curvature-compensated CMOS bandgap reference , 1983, IEEE Journal of Solid-State Circuits.

[44]  Terence B. Hook,et al.  Comment on “Channel Length and Threshold Voltage Dependence of a Transistor Mismatch in a 32-nm HKMG Technology” , 2011 .

[45]  D.K. Su,et al.  A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[46]  J. D. van der Tang.  High-Frequency Oscillator Design for Integrated Transceivers , 2003 .

[47]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[48]  Michiel Steyaert,et al.  Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages , 1994, IEEE J. Solid State Circuits.

[49]  H. P. Tuinhout.  Improving BiCMOS technologies using BJT parametric mismatch characterisation , 2003, 2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440).

[50]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[51]  W.C. Black,et al.  Technological design considerations for monolithic MOS switched-capacitor filtering systems , 1983, Proceedings of the IEEE.

[52]  M. Vertregt,et al.  CMOS technology for mixed signal ICs , 1997 .

[53]  Phillip E Allen,et al.  CMOS Analog Circuit Design , 1987 .

[54]  E. M. Cherry,et al.  The Design of Wide-Band Transistor Feedback Amplifiers , 1963 .

[55]  W. R. Bennett,et al.  Spectra of quantized signals , 1948, Bell Syst. Tech. J..

[56]  J. Kostamovaara,et al.  A CMOS time-to-digital converter with better than 10 ps single-shot precision , 2006, IEEE Journal of Solid-State Circuits.

[57]  L. J. V. D. Pauw.  A METHOD OF MEASURING SPECIFIC RESISTIVITY AND HALL EFFECT OF DISCS OF ARBITRARY SHAPE , 1991 .

[58]  M.J.M. Pelgrom,et al.  An algorithmic 15-bit CMOS digital-to-analog converter , 1988 .

[59]  Kenneth W. Martin,et al.  Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters , 1981 .

[60]  C.-K.K. Yang,et al.  Offset compensation in comparators with minimum input-referred supply noise , 2004, IEEE Journal of Solid-State Circuits.

[61]  Joel Max,et al.  Quantizing for minimum distortion , 1960, IRE Trans. Inf. Theory.

[62]  Y. Akazawa,et al.  Jitter analysis of high-speed sampling systems , 1990 .

[63]  Bang-Sup Song,et al.  A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter , 1988 .

[64]  Rudy J. van de Plassche,et al.  Dynamic element matching for high-accuracy monolithic D/A converters , 1976 .

[65]  Hae-Seung Lee,et al.  A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[66]  M. Clara,et al.  Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[67]  Michiel Steyaert,et al.  Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter , 2003 .

[68]  Robert H. Walden,et al.  Analog-to-digital converter survey and analysis , 1999, IEEE J. Sel. Areas Commun..

[69]  R. van Langevelde,et al.  RF-CMOS performance trends , 2001 .

[70]  Bruce A. Wooley,et al.  A third-order sigma-delta modulator with extended dynamic range , 1994 .

[71]  William Redman-White.  A high bandwidth constant g/sub m/ and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems , 1997 .

[72]  J.R. Brews.  MOSFET hand analysis using BSIM , 2006, IEEE Circuits and Devices Magazine.

[73]  Akira Matsuzawa,et al.  A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC , 1993 .

[74]  Georges Gielen,et al.  A 14-bit intrinsic accuracy Q2 random walk CMOS DAC , 1999, IEEE J. Solid State Circuits.

[75]  P.J.A. Naus,et al.  A CMOS Stereo 16 Bit D/A Converter for Digital Audio , 1986, ESSCIRC '86: Twelfth European Solid-State Circuits Conference.

[76]  J. Johnson,et al.  Lateral ion implant straggle and mask proximity effect , 2003 .

[77]  G. Gildenblat,et al.  PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation , 2006, IEEE Transactions on Electron Devices.

[78]  P. Stolk,et al.  Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[79]  B.K. Ahuja,et al.  An improved frequency compensation technique for CMOS operational amplifiers , 1983, IEEE Journal of Solid-State Circuits.

[80]  I. Mehr,et al.  A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC , 2000 .

[81]  Mohammed Ismail,et al.  Statistical modeling of device mismatch for analog MOS integrated circuits , 1992 .

[82]  Wenhua Yang,et al.  A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input , 2001, IEEE J. Solid State Circuits.

[83]  H. Reyhani,et al.  A 5 V, 6-b, 80 Ms/s BiCMOS flash ADC , 1994 .

[84]  Johan H. Huijsing,et al.  A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator , 2001 .

[85]  O.J.A.P. Nys,et al.  An analysis of dynamic element matching techniques in sigma-delta modulation , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[86]  K. Takeuchi,et al.  Statistical Compact Model Parameter Extraction by Direct Fitting to Variations , 2008, IEEE Transactions on Electron Devices.

[87]  W. Sansen,et al.  A comparison of extraction techniques for threshold voltage mismatch , 2002, Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002..

[88]  R. Havens,et al.  Noise modeling for RF CMOS circuit simulation , 2003 .

[89]  Donald M. Hummels,et al.  The noise power ratio-theory and ADC testing , 2000, IEEE Trans. Instrum. Meas..

[90]  K. Nguyen,et al.  A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio , 2005, IEEE Journal of Solid-State Circuits.

[91]  Patrick G. Drennan,et al.  Implications of Proximity Effects for Analog Design , 2006, IEEE Custom Integrated Circuits Conference 2006.

[92]  E. Iroaga,et al.  A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling , 2007, IEEE Journal of Solid-State Circuits.

[93]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[94]  K. R. Lakshmikumar,et al.  Characterisation and modeling of mismatch in MOS transistors for precision analog design , 1986 .

[95]  Michael P. Flynn,et al.  A 9b 14µW 0.06mm2 PPM ADC in 90nm digital CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[96]  Eric A. M. Klumperink,et al.  Spurious-Free Dynamic Range of a Uniform Quantizer , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[97]  Maurits Ortmanns,et al.  A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[98]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[99]  D. Draxelmayr,et al.  A monolithic triple 8 bit CMOS video coder , 1990 .

[100]  S. M. Sze.  Physics of semiconductor devices /2nd edition/ , 1981 .

[101]  R.A. Blauschild,et al.  A new NMOS temperature-stable voltage reference , 1978, IEEE Journal of Solid-State Circuits.

[102]  P.J.A. Naus,et al.  Multi-bit oversampled ΣΔ A/D converters as front-end for CD-players , 1990, ESSCIRC '90: Sixteenth European Solid-State Circuits Conference.

[103]  Marcel J. M. Pelgrom,et al.  Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[104]  W. Rey.  Introduction to Robust and Quasi-Robust Statistical Methods , 1983 .

[105]  F. Forti,et al.  Measurement of MOS current mismatch in the weak inversion region , 1994, IEEE J. Solid State Circuits.

[106]  A. Asenov,et al.  Statistical Compact Model Parameter Extraction Strategy for Intrinsic Parameter Fluctuation , 2007 .

[107]  R. Roovers,et al.  A 12 b 50 M sample/s cascaded folding and interpolating ADC , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[108]  Jon W. Mark,et al.  A Nonuniform Sampling Approach to Data Compression , 1981, IEEE Trans. Commun..

[109]  B. Nauta,et al.  A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$ , 2009, IEEE Journal of Solid-State Circuits.

[110]  F. O. Eynde,et al.  A high-speed CMOS comparator with 8-b resolution , 1992 .

[111]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[112]  R. Gregor,et al.  On the relationship between topography and transistor matching in an analog CMOS technology , 1992 .

[113]  Gabor C. Temes,et al.  Design-oriented estimation of thermal noise in switched-capacitor circuits , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[114]  Harry Nyquist.  Certain Topics in Telegraph Transmission Theory , 1928 .

[115]  Willy Sansen,et al.  Matching Properties of Deep Sub-Micron MOS Transistors , 2005 .

[116]  S.P. Voinigescu,et al.  A 1 GHz Bandwidth Low-Pass $\Delta \Sigma$ ADC With 20–50 GHz Adjustable Sampling Rate , 2009, IEEE Journal of Solid-State Circuits.

[117]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[118]  Eric A. Vittoz,et al.  High-performance crystal oscillator circuits: theory and application , 1988 .

[119]  Michael P. Flynn,et al.  A SAR-Assisted Two-Stage Pipeline ADC , 2011, IEEE Journal of Solid-State Circuits.

[120]  S. Gambini,et al.  A 100KS/s 65dB DR Σ — Δ ADC with 0.65V supply voltage , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[121]  Robert Henderson,et al.  Dynamic element matching techniques with arbitrary noise shaping function , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[122]  M.J.M. Pelgrom,et al.  A Versatile Digital CMOS Video Delay Line with Embedded ADC, DAC and RAM , 1993, ESSCIRC '93: Nineteenth European Solid-State Circuits Conference.

[123]  Nelson M. Blachman,et al.  The intermodulation and distortion due to quantization of sinusoids , 1985, IEEE Trans. Acoust. Speech Signal Process..

[124]  E. Vittoz,et al.  An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications , 1995 .

[125]  Un-Ku Moon,et al.  An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain , 2008, IEEE Journal of Solid-State Circuits.

[126]  R. V. Veldhoven.  A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[127]  Ardie G. W. Venes,et al.  An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing , 1996 .

[128]  H. Inose,et al.  A Telemetering System by Code Modulation - Δ- ΣModulation , 1962, IRE Transactions on Space Electronics and Telemetry.

[129]  James H. Stathis,et al.  The negative bias temperature instability in MOS devices: A review , 2006, Microelectron. Reliab..

[130]  Robert W. Adams,et al.  Design and Implementation of an Audio 18-Bit Analog-to-Digital Converter Using Oversampling Techniques , 1986 .

[131]  Robert W. Brodersen,et al.  A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS , 2006 .

[132]  Poki Chen,et al.  A CMOS pulse-shrinking delay element for time interval measurement , 2000 .

[133]  H. van der Ploeg,et al.  A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[134]  P. Andricciola,et al.  The Temperature Dependence of Mismatch in Deep-Submicrometer Bulk MOSFETs , 2009, IEEE Electron Device Letters.

[135]  R.D. Middlebrook.  The general feedback theorem: a final solution for feedback systems , 2006, IEEE Microwave Magazine.

[136]  P. Senn,et al.  A 27-MHz digital-to-analog video processor , 1988 .

[137]  Y. Akazawa,et al.  Circuits to reduce distortion in the diode-bridge track-and-hold , 1993 .

[138]  James D. Meindl,et al.  Low power microelectronics: retrospect and prospect , 1995, Proc. IEEE.

[139]  G. Geelen,et al.  A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[140]  P.R. Gray,et al.  An integrated NMOS operational amplifier with internal compensation , 1976, IEEE Journal of Solid-State Circuits.

[141]  Emmanuel J. Candès,et al.  Robust uncertainty principles: exact signal reconstruction from highly incomplete frequency information , 2004, IEEE Transactions on Information Theory.

[142]  K. E. Kuijk,et al.  A precision reference voltage source , 1973 .

[143]  Robert G. Meyer,et al.  Relationship between frequency response and settling time of operational amplifiers , 1974 .

[144]  L. S. Milor,et al.  A tutorial introduction to research on analog and mixed-signal circuit testing , 1998 .

[145]  Henk Termeer,et al.  A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter , 1991 .

[146]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[147]  Hae-Seung Lee,et al.  Comparator-based switched-capacitor circuits for scaled CMOS technologies , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[148]  Francois Krummenacher,et al.  A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning , 1987, ESSCIRC '87: 13th European Solid-State Circuits Conference.

[149]  Michiel Steyaert,et al.  A high-speed 850-nm optical receiver front-end in 0.18-μm CMOS , 2006 .

[150]  B.M.J. Kup,et al.  A bit-stream digital-to-analog converter with 18-b resolution , 1991 .

[151]  Johan H. Huijsing,et al.  Precision Temperature Sensors in CMOS Technology , 2006 .

[152]  S. Kawahito,et al.  A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters , 2005, IEEE Journal of Solid-State Circuits.

[153]  Ho-Jun Song,et al.  A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFET's , 1993 .

[154]  K. Philips,et al.  A continuous-time sigma delta ADC with increased immunity to wide-band interferers , 2004 .

[155]  Barrie Gilbert,et al.  A precise four-quadrant multiplier with subnanosecond response , 1968, IEEE Solid-State Circuits Newsletter.

[156]  H. P. Tuinhout,et al.  Accurate capacitor matching measurements using floating gate test structures , 1995, Proceedings International Conference on Microelectronic Test Structures.

[157]  J. van den Homberg,et al.  PowerDAC: a single-chip audio DAC with a 70%-efficient power stage in 0.5 /spl mu/m CMOS , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[158]  W. Guggenbuhl,et al.  A high-swing, high-impedance MOS cascode circuit , 1990 .

[159]  P. R. Gray,et al.  Reference refreshing cyclic analog-to-digital and digital-to-analog converters , 1986 .

[160]  A. W. M. van den Enden,et al.  Discrete-time signal processing: An introduction , 1989 .

[161]  Sungkyung Park,et al.  A digital-to-analog converter based on differential-quad switching , 2002, IEEE J. Solid State Circuits.

[162]  H. Wallinga,et al.  Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model , 1989 .

[163]  Jieh-Tsorng Wu,et al.  A 100-MHz pipelined CMOS comparator , 1988 .

[164]  R. Castello,et al.  A ratio-independent algorithmic analog-to-digital conversion technique , 1984, IEEE Journal of Solid-State Circuits.

[165]  D. Leeson.  A simple model of feedback oscillator noise spectrum , 1966 .

[166]  H. P. Tuinhout.  Electrical characterisation of matched pairs for evaluation of integrated circuit technologies , 2005 .

[167]  G. Temes,et al.  Random errors in MOS capacitors , 1982 .

[168]  Bruce A. Wooley,et al.  A 2.5-V sigma-delta modulator for broadband communications applications , 2001 .

[169]  Gilles Sicard,et al.  A 120nm low power asynchronous ADC , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..

[170]  S. Veeraraghavan,et al.  Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors , 2007, 2007 IEEE International SOI Conference.

[171]  A. Dingwall,et al.  An 8-MHz CMOS subranging 8-bit A/D converter , 1985, IEEE Journal of Solid-State Circuits.

[172]  P.R. Gray,et al.  A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR , 2004, IEEE Journal of Solid-State Circuits.

[173]  B.A. Wooley,et al.  A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded $\Sigma \Delta$ Modulator , 2008, IEEE Journal of Solid-State Circuits.

[174]  K. Philips,et al.  A 3.3 mW /spl Sigma//spl Delta/ modulator for UMTS in 0.18 /spl mu/m CMOS with 70 dB dynamic range in 2 MHz bandwidth , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[175]  T. Sarkar,et al.  Multiconductor Transmission Lines In Multilayered Dielectric Media , 1984 .

[176]  J. H. Atherton,et al.  An offset reduction technique for use with CMOS integrated comparators and amplifiers , 1992 .

[177]  M. Meijer,et al.  Characterization of STI Edge Effects on CMOS Variability , 2009, IEEE Transactions on Semiconductor Manufacturing.

[178]  J.H. Huijsing,et al.  An IF-to-Baseband $\Sigma \Delta$ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range , 2007, IEEE Journal of Solid-State Circuits.

[179]  A. Tekin,et al.  A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[180]  A.-J. Annema,et al.  Low-power bandgap references featuring DTMOSTs , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[181]  Maarten Vertregt,et al.  A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[182]  G. Temes,et al.  Analog MOS Integrated Circuits for Signal Processing , 1986 .

[183]  Jan Craninckx,et al.  A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[184]  P.J. Hurst,et al.  Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA , 2009, IEEE Journal of Solid-State Circuits.

[185]  M. Unser.  Sampling-50 years after Shannon , 2000, Proceedings of the IEEE.

[186]  D.A. Hodges,et al.  All-MOS charge-redistribution analog-to-digital conversion techniques. II , 1975, IEEE Journal of Solid-State Circuits.

[187]  P.J. Hurst,et al.  A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration , 2004, IEEE Journal of Solid-State Circuits.

[188]  M. Steyaert,et al.  A 12 b 500 MSample/s current-steering CMOS D/A converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[189]  David A. Hodges,et al.  Charge circuits for analog LSI , 1978 .

[190]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[191]  B. Widrow.  A Study of Rough Amplitude Quantization by Means of Nyquist Sampling Theory , 1956 .

[192]  H. J. M. Veendrick,et al.  Deep-submicron CMOS ICs , 1998 .

[193]  Voicu Groza,et al.  High-resolution floating-point ADC , 2001, IEEE Trans. Instrum. Meas..

[194]  J. McCreary.  Matching properties, and voltage and temperature dependence of MOS capacitors , 1981 .

[195]  M. Vertregt,et al.  A 25-Ms/s 8-bit CMOS A/D converter for embedded application , 1994 .

[196]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.

[197]  R. van de Grift,et al.  An 8-bit video ADC incorporating folding and interpolation techniques , 1987 .

[198]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[199]  R. J. van de Plassche,et al.  A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF , 1999, IEEE J. Solid State Circuits.

[200]  Abbas El Gamal,et al.  On incremental sigma-delta modulation with optimal filtering , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[201]  Michiel Steyaert,et al.  A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter , 2001 .

[202]  K. Makinwa,et al.  A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios , 2009, IEEE Journal of Solid-State Circuits.

[203]  Byung-Moo Min,et al.  A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC , 2003, IEEE J. Solid State Circuits.

[204]  David A. Johns,et al.  Analog Integrated Circuit Design , 1996 .

[205]  Bin-Da Liu,et al.  A new successive approximation architecture for low-power low-cost CMOS A/D converter , 2003, IEEE J. Solid State Circuits.

[206]  W. Ellersick,et al.  GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

[207]  K.C.-H. Chao,et al.  A higher order topology for interpolative modulators for oversampling A/D converters , 1990 .

[208]  Ronald W. Knepper.  Dynamic depletion mode: an E/D MOSFET circuit method for improved performance , 1978 .

[209]  P. Vorenkamp,et al.  Fully bipolar, 120-Msample/s 10-b track-and-hold circuit , 1992 .

[210]  M. Vertregt.  The analog challenge of nanometer CMOS , 2006, 2006 International Electron Devices Meeting.

[211]  Michiel Steyaert,et al.  Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits , 1996, Proceedings of Custom Integrated Circuits Conference.

[212]  Yannis Tsividis.  Design considerations in single-channel MOS analog integrated circuits-a tutorial , 1978 .

[213]  P.R. Gray,et al.  MOS operational amplifier design-a tutorial overview , 1982, IEEE Journal of Solid-State Circuits.

[214]  W. Thommen,et al.  An improved low power crystal oscillator , 1999, Proceedings of the 25th European Solid-State Circuits Conference.

[215]  M. F. Tompsett,et al.  A 10-b 15-MHz CMOS recycling two-step A/D converter , 1990 .

[216]  B. Hoefflinger,et al.  A 5-bit building block for 20 MHz A/D converters , 1981, IEEE Journal of Solid-State Circuits.

[217]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[218]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[219]  Sameer R. Sonkusale,et al.  An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[220]  R. Meyer,et al.  A one-pin crystal oscillator for VLSI circuits , 1984, IEEE Journal of Solid-State Circuits.

[221]  J.J.F. Rijns.  CMOS Low-Distortion High-Frequency Variable-Gain Amplifier , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.

[222]  H. P. Tuinhout,et al.  Design and characterisation of a high precision resistor ladder test structure , 2002, ICMTS 2002.

[223]  K. Bult,et al.  An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2 , 1997, IEEE J. Solid State Circuits.

[224]  D.K. Su,et al.  A 0.7-V 870-$\mu$ W Digital-Audio CMOS Sigma-Delta Modulator , 2009, IEEE Journal of Solid-State Circuits.

[225]  C.-H. Lin,et al.  A 10 b 250 M sample/s CMOS DAC in 1 mm/sup 2/ , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[226]  J. F. Dickson,et al.  On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique , 1976 .

[227]  William Redman-White,et al.  A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation , 2001 .

[228]  Gabor C. Temes,et al.  Oversampling delta-sigma data converters : theory, design, and simulation , 1992 .

[229]  Jonathan Borremans,et al.  A 2.4 GHz Low-Power Sixth-Order RF Bandpass $\Delta\Sigma$ Converter in CMOS , 2009, IEEE Journal of Solid-State Circuits.

[230]  J. Schoeff,et al.  An inherently monotonic 12 bit DAC , 1979, IEEE Journal of Solid-State Circuits.

[231]  K. Watanabe,et al.  Switched-capacitor algorithmic digital-to-analog converters , 1986 .

[232]  J. Seto.  The electrical properties of polycrystalline silicon films , 1975 .

[233]  Timo Rahkonen,et al.  The use of stabilized CMOS delay lines for the digitization of short time intervals , 1993 .

[234]  P. J. Green,et al.  Overview of IEEE-STD-1241 "standard for terminology and test methods for analog-to-digital converters" , 1999, IMTC/99. Proceedings of the 16th IEEE Instrumentation and Measurement Technology Conference (Cat. No.99CH36309).

[235]  John Vanderkooy,et al.  A theory of nonsubtractive dither , 2000, IEEE Trans. Signal Process..

[236]  D.W.J. Groeneveld,et al.  A low-power stereo 16-bit CMOS D/A converter for digital audio , 1988 .

[237]  F. Klaassen,et al.  On the temperature coefficient of the MOSFET threshold voltage , 1986 .

[238]  R. J. Widlar,et al.  New developments in IC voltage regulators , 1970 .

[239]  Hans Tuinhout,et al.  High precision on-wafer backend capacitor mismatch measurements using a benchtop semiconductor characterization system , 2009, 2009 IEEE International Conference on Microelectronic Test Structures.

[240]  Rolf Unbehauen.  Synthese elektrischer Netzwerke , 1972 .

[241]  S. P. Lloyd,et al.  Least squares quantization in PCM , 1982, IEEE Trans. Inf. Theory.

[242]  Randall L. Geiger,et al.  Current Mirror Layout Strategies for Enhancing Matching Performance , 2001 .

[243]  B.M.J. Kup,et al.  A Monolithic Dual 16 Bit D/A Converter , 1985, ESSCIRC '85: 11th European Solid-State Circuits Conference.

[244]  Bram Nauta,et al.  A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter , 1995 .

[245]  D. F. Berndt,et al.  Inductor simulation using a single unity gain amplifier , 1969 .

[246]  C. S. Petrie,et al.  A multibit sigma-delta ADC for multimode receivers , 2003, IEEE J. Solid State Circuits.

[247]  W. Groeneveld,et al.  A self calibration technique for monolithic high-resolution D/A converters , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[248]  Maarten Vertregt,et al.  Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures , 2001 .

[249]  M. Pelgrom,et al.  A CCD Delay Line for Video Applications , 1987, IEEE Transactions on Consumer Electronics.

[250]  Robert H. M. van Veldhoven,et al.  A 56 mW Continuous-Time Quadrature Cascaded $\Sigma\Delta$ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band , 2007, IEEE Journal of Solid-State Circuits.

[251]  L. R. Carley,et al.  A noise-shaping coder topology for 15+ bit converters , 1989 .

[252]  Robert G. Meyer,et al.  Analysis and Design of Analog Integrated Circuits , 1993 .

[253]  G. Hoogzaad,et al.  A 65 mW 10 b 40 Msample/s BiCMOS Nyquist ADC in 0.8 mm/sup 2/ , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[254]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[255]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[256]  H.P. Tuinhout,et al.  Measuring the span of stress asymmetries on high-precision matched devices , 2004, Proceedings of the 2004 International Conference on Microelectronic Test Structures (IEEE Cat. No.04CH37516).

[257]  A. Brokaw,et al.  A simple three-terminal IC bandgap reference , 1974 .

[258]  M. Pelgrom,et al.  Monitors for a signal integrity measurement system , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.

[259]  Bruce A. Wooley,et al.  A CMOS oversampling D/A converter with a current-mode semi-digital reconstruction filter , 1993 .

[260]  G. Geelen,et al.  A fast-settling CMOS op amp for SC circuits with 90-dB DC gain , 1990 .

[261]  M. Bolatkale,et al.  A 4 GHz Continuous-Time $\Delta\Sigma$ ADC With 70 dB DR and $-$74 dBFS THD in 125 MHz BW , 2011, IEEE Journal of Solid-State Circuits.

[262]  P. G. Drennan.  Diffused resistor mismatch modeling and characterization , 1999, Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024).

[263]  K. Kattmann,et al.  A Technique For Reducing Differential Non-linearity Errors In Flash A/D Converters , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[264]  John Vanderkooy,et al.  Why 1-Bit Sigma-Delta Conversion is Unsuitable for High-Quality Applications , 2001 .