20-40 Gbit/s GaAs-HEMT chip set for optical data receiver

Using our 0.2 and 0.3 μm AlGaAs/GaAs/AlGaAs quantum well HEMT technology, we have developed a chip set for 20–40 Gbit/s fiber-optical digital transmission systems. In this paper we describe nine analog and digital receiver ICs: a 22 GHz high-gain transimpedance amplifier, a 20 Gbit/s OEIC front-end optical receiver, a 25 Gbit/s automatic-gain-control amplifier, a limiting amplifier with a differential gain of 26 dB and a bandwidth of 27.7 GHz, a 20–40 Gbit/s clock recovery, a 20 Gbit/s low-power Master-Slave-D-Flipflop with 24 mW power dissipation, a parallel data decision and a 1:4 demultiplexer, both for bit rates of 40 Gbit/s, and a 30 GHz static frequency divider, respectively. All chips were characterized on wafers with 50 Ω coplanar test probes.

[1]  M. Rieger-Motzer,et al.  Circuit techniques for 10 and 20 Gb/s clock recovery using a fully balanced narrowband regenerative frequency divider with 0.3 /spl mu/m HEMTs [SDH/SONET] , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  T. F. Meister,et al.  20 Gbit/s transimpedance preamplifier and modulator driver in SiGe bipolar technology , 1997 .

[3]  Wolfgang Bronner,et al.  45 Gbit/s AlGaAs/GaAs HEMT multiplexer IC , 1997 .

[4]  U. Langmann,et al.  Design of a low-power 10 Gb/s Si bipolar 1:16-demultiplexer IC , 1996 .

[5]  Kikuo Okuyama,et al.  A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer , 1992 .

[6]  Wolfgang Bronner,et al.  28-51 GHz dynamic frequency divider based on 0.15 mu m T-gate Al/sub 0.2/Ga/sub 0.8/As/In/sub 0.25/Ga/sub 0.75/As MODFETs , 1993 .

[7]  K. Runge,et al.  40 Gbit/s AlGaAs/GaAs HBT 4:1 multiplexer IC , 1995 .

[8]  D. Clawin,et al.  Si bipolar 14 Gb/s 1:4-demultiplexer IC for system applications , 1996 .

[9]  Wolfgang Bronner,et al.  Mixed signal integrated circuits based on GaAs HEMTs , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Mau-Chung Frank Chang,et al.  11.6-GHz 1:4 regenerating demultiplexer with bit-rotation control and 6.1-GHz auto-latching phase-aligner ICs using AlGaAs/GaAs HBT technology , 1992 .

[11]  Y. Imai,et al.  A 15-GHz AlGaAs/GaAs HBT limiting amplifier with low phase deviation , 1991, [1991] GaAs IC Symposium Technical Digest.

[12]  B.G. Bosch,et al.  Gigabit electronics—A review , 1979, Proceedings of the IEEE.

[13]  Z.-G. Wang,et al.  20-40 Gbit/s 0.2 /spl mu/m GaAs HEMT chip set for optical data receiver , 1996, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium. 18th Annual Technical Digest 1996.

[14]  Wolfgang Bronner,et al.  Monolithic 10 channel 10 Gbit/s amplifier array using 0.3 /spl mu/m AlGaAs/GaAs-HEMTs , 1996 .

[15]  Z.-G. Wang,et al.  Low power data decision IC for 20-40 Gbit/s data links using 0.2 /spl mu/m AlGaAs/GaAs HEMTs , 1996 .

[16]  Josef Bock,et al.  46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology , 1996 .

[17]  Behzad Razavi.  A 2.5-Gb/s 15-mW clock recovery circuit , 1996 .

[18]  Noboru Ishihara,et al.  Over-10-Gb/s IC's for future lightwave communications , 1994 .

[19]  Eiichi Sano,et al.  A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET , 1995 .

[20]  H. Ichino,et al.  A low-power bipolar circuit for Gbit/s LSIs-current mirror control logic (CMCL) , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[21]  Michael Schlechtweg,et al.  Coplanar millimeter-wave ICs for W-band applications using 0.15 μm pseudomorphic MODFETs , 1996, IEEE J. Solid State Circuits.

[22]  Wolfgang Bronner,et al.  Low power 20 Gbit/s data decision and 17 GHz static frequency divider ICs with 1.5 V supply voltage , 1997 .

[23]  Z. H. Lao,et al.  A 20-Gb/s silicon bipolar 1:4-demultiplexer IC , 1994 .

[24]  E. L. Hudson,et al.  A variable delay line PLL for CPU-coprocessor synchronization , 1988 .

[25]  J. Hauenschild,et al.  A 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer in a standard plastic package with external VCO , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[26]  D. Clawin,et al.  A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems , 1995 .

[27]  Michael Schlechtweg,et al.  35-GHz static and 48-GHz dynamic frequency divider ICs using 0.2-/spl mu/m AlGaAs/GaAs-HEMTs , 1997 .

[28]  D. Clawin,et al.  Silicon bipolar 14 Gb/s 1:4-demultiplexer IC regarding system requirements , 1994, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting.

[29]  Z.-G. Wang,et al.  10 and 20 Gbit/s clock recovery GaAs IC with 288° phase-shifting function , 1996 .

[30]  T. Jakobus,et al.  E-Beam Direct-Write in a Dry-Etched Recess Gate HEMT Process for GaAs/AlGaAs Circuits , 1990 .

[31]  Hans-Martin Rein,et al.  Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s , 1996, IEEE J. Solid State Circuits.

[32]  D. Clawin,et al.  Silicon bipolar 1:16-demultiplexer for 10 Gbit/s fibre optic communication system , 1994 .