Probabilistic Error Modeling for Approximate Adders

Approximate adders are widely being advocated as a means to achieve performance gain in error resilient applications. In this paper, a generic methodology for analytical modeling of probability of occurrence of error and the Probability Mass Function (PMF) of error value in a selected class of approximate adders is presented, which can serve as performance metrics for the comparative analysis of various adders and their configurations. The proposed model is applicable to approximate adders that comprise of sub-adder units of uniform as well as non-uniform lengths. Using a systematic methodology, we derive closed form expressions for the probability of error for a number of state-of-the-art high-performance approximate adders. The probabilistic analysis is carried out for arbitrary input distributions. It can be used to study the dependence of error statistics in an adder’s output on its configuration and input distribution. Moreover, it is shown that by building upon the proposed error model, we can estimate the probability of error in circuits with multiple approximate adders. We also demonstrate that, using the proposed analysis, the comparative performance of different approximate adders can be correctly predicted in practical applications of image processing.

[1]  Yi-Ming Yang,et al.  High-Performance Low-Power Carry Speculative Addition With Variable Latency , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Fabrizio Lombardi,et al.  A Comparative Review and Evaluation of Approximate Adders , 2015, ACM Great Lakes Symposium on VLSI.

[3]  Gang Wang,et al.  Enhanced low-power high-speed adder for error-tolerant application , 2009, 2010 International SoC Design Conference.

[4]  Fabrizio Lombardi,et al.  A low-power, high-performance approximate multiplier with configurable partial error recovery , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[6]  Fabrizio Lombardi,et al.  An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders , 2015, IEEE Transactions on Computers.

[7]  A. Leon-Garcia Probability, statistics, and random processes for electrical engineering , 2008 .

[8]  Kartikeya Bhardwaj,et al.  Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems , 2014, Fifteenth International Symposium on Quality Electronic Design.

[9]  Andreas Gerstlauer,et al.  Approximate logic synthesis under general error magnitude and frequency constraints , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  Kaushik Roy,et al.  Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Kaushik Roy,et al.  MACACO: Modeling and analysis of circuits for approximate computing , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Shih-Lien Lu Speeding Up Processing with Approximation Circuits , 2004, Computer.

[13]  Kaushik Roy,et al.  Substitute-and-simplify: A unified design paradigm for approximate and quality configurable circuits , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Fabrizio Lombardi,et al.  Approximate XOR/XNOR-based adders for inexact computing , 2013, 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013).

[15]  Paolo Ienne,et al.  Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design , 2008, 2008 Design, Automation and Test in Europe.

[16]  Ku He,et al.  Modeling and synthesis of quality-energy optimal approximate adders , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Andrew B. Kahng,et al.  Accuracy-configurable adder for approximate arithmetic designs , 2012, DAC Design Automation Conference 2012.

[18]  Puneet Gupta,et al.  Trading Accuracy for Power in a Multiplier Architecture , 2011, J. Low Power Electron..

[19]  Rakesh Kumar,et al.  On reconfiguration-oriented approximate adder design and its application , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[20]  Yang Liu,et al.  Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Peter J. Varman,et al.  High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[22]  Zhi-Hui Kong,et al.  Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Muhammad Shafique,et al.  An area-efficient consolidated configurable error correction for approximate hardware accelerators , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[24]  Muhammad Shafique,et al.  A low latency generic accuracy configurable adder , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[25]  Kaushik Roy,et al.  IMPACT: IMPrecise adders for low-power approximate computing , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[26]  Fabrizio Lombardi,et al.  New Metrics for the Reliability of Approximate and Probabilistic Adders , 2013, IEEE Transactions on Computers.

[27]  Antonio Ortega,et al.  NEW QUALITY METRICS FOR MULTIMEDIA COMPRESSION USING FAULTY HARDWARE In , 2006 .