论文信息 - Design of a 10-b pipelined ADC without calibration

Design of a 10-b pipelined ADC without calibration

This paper describes the design of a 10-b fully differential pipelined analog-to-digital converter (ADC). The pipelined ADC has been designed using the switched-opamp technique without calibration in a 0.7 µm CMOS process for sensor applications. Low power consumption is one of the most important issues. An operational amplifier (opamp) sharing technique was used to decrease the power usage.

Jiri Haze | Vilem Kledrowetz

[1] Imran Ahmed. Pipelined ADC Design and Enhancement Techniques , 2010 .

[2] Takashi Oshima,et al. 23-mW 50-MS/s 10-bit pipeline A/D converter with nonlinear LMS foreground calibration , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[3] Chang-Hyuk Cho. A Power Optimized Pipelined Analog-to-Digital Converter Design in Deep Sub-Micron CMOS Technology , 2005 .

[4] El-Sayed Eid,et al. Design of an 8-bit pipelined ADC with lower than 0.5 LSB DNL and INL without calibration , 2009, 2009 4th International Design and Test Workshop (IDT).

[5] Jiri Haze,et al. Analysis of non-ideal effects of pipelined ADC by using MATLAB-Simulink , 2010 .

[6] W. Zhang,et al. Switch-embedded opamp-sharing MDAC with dual-input OTA in pipelined ADC , 2010 .

[7] Kari Halonen,et al. CMOS dynamic comparators for pipeline A/D converters , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).