Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform

A low cost 28Gbits/s Silicon Photonics platform using 300mm SOI wafers is demonstrated. Process, 3D integration of Electronic and Photonic ICs, device performance, circuit results and low cost packaging are discussed.

[1]  Enrico Temporiti,et al.  A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[2]  Antonio Santipo,et al.  Hybrid silicon photonic circuits and transceiver for 56Gb/s NRZ 2.2km transmission over single mode fiber , 2014, 2014 The European Conference on Optical Communication (ECOC).

[3]  B. Ebersberger,et al.  Cu pillar bumps as a lead-free drop-in replacement for solder-bumped, flip-chip interconnects , 2008, 2008 58th Electronic Components and Technology Conference.

[4]  G. Masini,et al.  A multi-wavelength 3D-compatible silicon photonics platform on 300mm SOI wafers for 25Gb/s applications , 2013, 2013 IEEE International Electron Devices Meeting.

[5]  Mark Peterson,et al.  Advantages of CMOS photonics for future transceiver applications , 2010, 36th European Conference and Exhibition on Optical Communication.

[6]  Yann Lamy,et al.  Copper pillar interconnect capability for mmwave applications in 3D integration technology , 2013 .

[7]  Min Yang,et al.  A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications , 2012, 2012 International Electron Devices Meeting.

[8]  S. G. Kim,et al.  Integration of silicon photonics into DRAM process , 2013, 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC).