Multi-Bit Low Redundancy Error control with Parity Sharing for NoC Interconnects

Network-on-Chips (NoCs) have become an efficient solution to overcome the issues of the bus-based architectures in System-on-Chips (SoCs). In the era of deep sub-micron technology, many systems are getting affected by number of errors which cause NoC failure. In order to overcome this issue, an Error Detection and Correction (EDC) coding technique is needed. So, this paper presents a Multi-bit Low Redundancy Error control with Parity Sharing (MLREPS) coding technique for NoC Interconnects. In this coding technique, a simple parity check code is used to achieve error correction with small area, power and delay overhead. In addition, it achieves higher reliability. Simulated results of the MLREPS coding technique are compared with the 2D fault coding technique. Analysis shows that the proposed coding technique is better than the existing technique in terms of residual error probability, link power consumption and swing voltage of the link by 42.2%, 77% and 55.5%.

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