Design and optimization of an integrated 1GHz PLL IP for microprocessors

A high speed phase locked loop is analyzed from the system point of view and different trade-offs in designing a stable low noise clock generator IP in microprocessors is discussed. A new design methodology for loop filter is presented to avoid using large on-chip capacitor in a standard logic CMOS process. Based on SMIC 0.18/spl mu/m 1P4M logic process, the PLL operates up to 1.1 GHz, the root mean square of cycle-to-cycle jitter is 9.1 ps at 1 GHz output with 26.1 mW power consumption by post-layout simulation.