A 155-MB/s 32*32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system. >
[1]
M. Nakamae,et al.
A 40 GHz f/sub T/ Si bipolar transistor LSI technology
,
1989,
International Technical Digest on Electron Devices Meeting.
[2]
M. Sugiyama,et al.
BSA Technology for sub-100nm deep base bipolar transistors
,
1987,
1987 International Electron Devices Meeting.
[3]
M. Nakamae,et al.
Bipolar VLSI memory cell technology utilizing BPSG-filled trench isolation
,
1989
.
[4]
Ching-Te Chuang,et al.
A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage
,
1989
.
[5]
T. Takeuchi,et al.
A time-division broadband switching network using a frame synchronization technique
,
1988,
IEEE International Conference on Communications, - Spanning the Universe..