Exploring Wireless Technology for Off-Chip Memory Access

The trend of shifting from multi-core to many-core processors is exceeding the data-carrying capacity of the traditional on-chip communication fabric. While the importance of the on-chip communication paradigm cannot be denied, the off-chip memory access latency is fast becoming an important challenge. As more memory intensive applications are developed, off-chip memory access will limit the performance of chip multi-core processors (CMPs). However, with the shrinkage of transistor dimension, the energy consumption and the latency of the traditional metallic interconnects are increasing due to smaller wire widths, longer wire lengths, and complex multi-hop routing requirements. In contrast, emerging wireless technology requires lower energy with single-hop communication, albeit with limited bandwidth (at a 60 GHz center frequency). In this paper, we have proposed several hybrid-wireless architectures to access off-chip memory by exploiting frequency division multiplexing (FDM), time division multiplexing (TDM), and space division multiplexing (SDM) techniques. We explore the design-space of building hybrid-wireless interconnects by considering conservative and aggressive wireless bandwidths and directionality. Our hybrid-wireless architectures require a maximum of two hops and show 10.91% reduction in execution time compared to a baseline metallic architecture. In addition, the proposed hybrid-wireless architectures show on an average 62.07% and 32.52% energy per byte improvement over traditional metallic interconnects for conservative and aggressive off-chip metallic link energy-efficiency respectively. Nevertheless, the proposed hybrid-wireless architectures incur an area overhead due to the higher transceiver area requirement.

[1]  Jason Cong,et al.  A scalable micro wireless interconnect structure for CMPs , 2009, MobiCom '09.

[2]  Avinash Karanth Kodi,et al.  Antennas and Channel Characteristics for Wireless Networks on Chips , 2017, Wireless Personal Communications.

[3]  Ahmed Louri,et al.  OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures , 2015, 2015 IEEE 23rd Annual Symposium on High-Performance Interconnects.

[4]  Amlan Ganguly,et al.  An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links , 2015, NOCS.

[5]  Natalie D. Enright Jerger,et al.  Achieving predictable performance through better memory controller placement in many-core CMPs , 2009, ISCA '09.

[6]  Uri C. Weiser,et al.  Semantic locality and context-based prefetching using reinforcement learning , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[7]  O Seongil,et al.  Row-buffer decoupling: A case for low-latency DRAM microarchitecture , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[8]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[9]  Kiyoung Choi,et al.  PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[10]  David W. Matolak,et al.  Energy-efficient adaptive wireless NoCs architecture , 2013, 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS).

[11]  Christof Teuscher,et al.  Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems , 2011, IEEE Transactions on Computers.

[12]  Mahmut T. Kandemir,et al.  Addressing End-to-End Memory Access Latency in NoC-Based Multicores , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[13]  Yong Liu,et al.  An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects , 2012, IEEE Journal of Solid-State Circuits.

[14]  Stefanos Kaxiras,et al.  Callback: Efficient synchronization without invalidation with a directory just for spin-waiting , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[15]  Chen Sun,et al.  DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[16]  David W. Matolak,et al.  Kilo-core Wireless Network-on-Chips (NoCs) Architectures , 2015, NANOCOM.

[17]  김장우,et al.  A fully associative, tagless DRAM cache , 2015 .

[18]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[19]  David Kaeli,et al.  The Multi2Sim Simulation Framework: A CPU-GPU Model for Heterogeneous Computing , 2011 .

[20]  Bruce Jacob,et al.  Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[21]  TN-41-13: DDR3 Point-to-Point Design Support , 2013 .