Thermal issues in stacked die packages

After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-the-art and the major issues of compact thermal modeling of stacked die packages.

[1]  M. Rencz,et al.  Determining partial thermal resistances with transient measurements, and using the method to detect die attach discontinuities , 2002, Eighteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings 2002 (Cat.No.02CH37311).

[2]  M. Rencz,et al.  A procedure to correct the error in the structure function based thermal measuring methods , 2004, Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545).

[3]  K. Srihari,et al.  Voids in thermal interface material layers and their effect on thermal performance , 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

[4]  Andras Poppe,et al.  Testing the Die Attach Quality of 3D Stacked Dies , 2004 .

[6]  Yinan Wu,et al.  Modeling of stacked packaging thermal performance in module/system environment , 2005, Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005..

[7]  J. Brunner,et al.  Advanced wire bond looping technology for emerging packages , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

[8]  C.W.C. Lin,et al.  3D stacked packages with bumpless interconnect technology , 2003, IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003..

[9]  P. Stehouwer,et al.  Creation and evaluation of compact models for thermal characterisation using dedicated optimisation software , 1999, Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306).

[10]  Clemens J. M. Lasance.  Recent progress in compact thermal models , 2003, Ninteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium, 2003..

[11]  M. Rencz,et al.  Structure function evaluation of stacked dies , 2004, Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545).

[12]  D.Y.R. Chong,et al.  Thermal management and characterization of flip chip BGA packages , 2004, Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971).

[13]  V. Székely,et al.  Fine structure of heat flow path in semiconductor devices: a measurement and identification method , 1988 .

[14]  Olivier Vendier,et al.  Thermal modeling and management in ultrathin chip stack technology , 2002 .

[15]  H. Pape,et al.  Generation and verification of boundary independent compact thermal models for active components according to the DELPHI/SEED methods , 1999, Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306).

[16]  M. Rencz,et al.  Die attach quality control of 3D stacked dies , 2004, IEEE/CPMT/SEMI 29th International Electronics Manufacturing Technology Symposium (IEEE Cat. No.04CH37585).

[17]  L. Zhang,et al.  Thermal characterization of stacked-die packages , 2004, Twentieth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (IEEE Cat. No.04CH37545).

[18]  Robert J. Wojnarowski,et al.  Advanced 3-D stacked technology , 2003, Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003).