Semiconductor memory device and method of generating reference voltage for operations of the semiconductor memory device
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A semiconductor memory device according to the present invention includes a reference voltage generator which includes: a first decoder which generates a default setting signal based on a reset signal and a clock activation signal in a power-up operation; a second decoder which generates a reference voltage setting signal based on the default setting signal; and a reference voltage generator which includes a reference voltage provider generating an internal reference voltage based on the reference voltage setting signal.