A New Matrix Vector Product Systolic Array

Abstract The array size of parallel processor implementations designed by the data dependence method is not optimal. Nonlinear transformations applied on some symmetric transformations offer more efficient arrays and smaller processor array size. The Kung-Leiserson matrix vector multiplication linear systolic array is used as an example of a symmetric linear mapping. Two procedures are introduced to express the folding idea by choosing different axes of symmetry and nonlinear transformations. The first procedure that uses folding and retiming results in an irregular data flow. The folding is reallocated in the second procedure which results in a regular data flow. The new systolic implementations have many advantages over the conventional such as more efficient processor use, circular data flow, one I/O processor and the most important: use of 40% up to 50% less processors . The processors are provided by an extra switching function between the inputs and outputs being the only disadvantage.