Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays

Recently, single-electron transistors (SETs) have been attracting substantial attention and are considered candidate devices for future integrated circuits due to their ultralow power consumption. To realize SETs, a binary decision diagram-based SET array is proposed as a suitable candidate for implementing Boolean circuits. Then, some works started developing computer-aided design techniques for this new architecture. However, most of them focused on the development of mapping techniques. How to verify the mapping results is still an open problem. Thus, in this paper, we address this problem and develop a satisfiability (SAT)-based verification method. We propose a transformation approach to model the functionality of a mapped SET array as a conjunctive normal form formula. Then, the problem that whether the SET array is functionally equivalent to its specification circuit can be solved with a SAT solver. The experimental results show that the proposed method can successfully verify correct and incorrect SET array implementations with reasonable verification time.

[1]  Kazuhiko Matsumoto,et al.  Room temperature operation of a single electron transistor made by the scanning tunneling microscope nanooxidation process for the TiOx/Ti system , 1996 .

[2]  Yoshihito Amemiya,et al.  Single-electron logic device based on the binary decision diagram , 1997 .

[3]  Vinay Saripalli,et al.  Device circuit co-design using classical and non-classical III–V Multi-Gate Quantum-Well FETs (MuQFETs) , 2011, 2011 International Electron Devices Meeting.

[4]  C. Dekker,et al.  Carbon Nanotube Single-Electron Transistors at Room Temperature , 2001, Science.

[5]  Zahid A. K. Durrani,et al.  Room temperature nanocrystalline silicon single-electron transistors , 2003 .

[6]  Stephen Y. Chou,et al.  Silicon single-electron quantum-dot transistor switch operating at room temperature , 1998 .

[7]  M. H. Devoret,et al.  Introduction to Single Charge Tunneling , 1992 .

[8]  G. S. Tseitin.  On the Complexity of Derivation in Propositional Calculus , 1983 .

[9]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[10]  Narayanan Vijaykrishnan,et al.  On reconfigurable Single-Electron Transistor arrays synthesis using reordering techniques , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[11]  Vinay Saripalli,et al.  Multi-Gate Modulation Doped In0.7Ga0.3 As Quantum Well FET for Ultra Low Power Digital Logic , 2011 .

[12]  Narayanan Vijaykrishnan,et al.  Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits , 2010, J. Low Power Electron..

[13]  Seiya Kasai,et al.  Fabrication of GaAs-based integrated 2-bit half and full adders by novel hexagonal BDD quantum circuit approach , 2001 .

[14]  Seiya Kasai,et al.  Hexagonal binary decision diagram quantum logic circuits using Schottky in-plane and wrap-gate control of GaAs and InGaAs nanowires , 2001 .

[15]  Yasuo Takahashi,et al.  Si-based ultrasmall multiswitching single-electron transistor operating at room-temperature , 2010 .

[16]  Narayanan Vijaykrishnan,et al.  Reconfigurable BDD based quantum circuits , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[17]  Shashi P. Karna,et al.  Room temperature operational single electron transistor fabricated by focused ion beam deposition , 2007 .

[18]  Ken Uchida,et al.  Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation , 2003 .

[19]  Narayanan Vijaykrishnan,et al.  A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays , 2013, JETC.

[20]  F. Ferrari,et al.  System-on-a-chip verification~methodology and techniques , 2002, IEEE Circuits and Devices Magazine.

[21]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.

[22]  Zhen Yao,et al.  Carbon Nanotube Single‐Electron Transistors at Room Temperature. , 2001 .

[23]  Narayanan Vijaykrishnan,et al.  Automated mapping for reconfigurable single-electron transistor arrays , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).