Performance-driven evaluation of bipolar analog layouts

An approach is described for evaluating the effect of an analog bipolar circuit's layout on its performance. The approach uses a combination of sensitivity analysis to determine the sensitivity of circuit performance on parametric component variations and parasitic elements. Rules of thumb are then used to detect whether the layout attempts to minimize these sensitivities. The approach has been implemented in a tool which has been integrated into the Berkeley OCT/VEM environment and tested using examples from industry.<<ETX>>