Design and Characterization of Third Generation Current Conveyor

This paper presents a low power low voltage positive third generation current conveyor using four simple first generation current conveyors. It is designed and simulated in a standard 0.18um TSMC 1P, 6M CMOS process. This current conveyor design with the help of design architect and IC station (mentor graphics). Its DC, AC and transient analysis is carried out with ELDO tool. Its pre layout and post layout results are also given.