A Design Methodology for Compact Integration of Wave Digital Filters

A top-down methodology for custom integration of Wave Digital filters is discussed. The design is supported by a CAD toolbox, which starts from filter specifications, uses a bit serial architecture and results in dense layout. This is demonstrated by a 3rd order elliptical filter chip, which works at a sampling rate of 312 Khz. The area is 1.8mm2 in 6¿m NMOS technology. As a result of scaling, pole-zero areas of 0.2mm2 can be expected for 3¿m technology.