A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors

Nonvolatile flip-flops (nvFFs) enable frequent-off processors to achieve fast power-off and wake-up time while maintaining critical local computing states through parallel data movement between volatile FFs and local nonvolatile memory (NVM) devices. However, current nvFFs face challenges in large store energy (<inline-formula> <tex-math notation="LaTeX">$\text{E}_{\mathrm {S}}$ </tex-math></inline-formula>) and long voltage stress time on the device (<inline-formula> <tex-math notation="LaTeX">$\text{T}_{\mathrm {STRESS}}$ </tex-math></inline-formula>), due to wide distribution in the write time of NVM device as well as unnecessary writes. Moreover, heavy parasitic load on the power rail cause long wake-up time for restoring data from NVM to FFs. This paper proposes the resistive RAM (ReRAM)-based nvFF with self-write termination (SWT) and reduced loading on power rail to: 1) reduce 93+% waste of <inline-formula> <tex-math notation="LaTeX">$\text{E}_{\mathrm {S}}$ </tex-math></inline-formula> from fast switching or matched cells; 2) suppress endurance and reliability degradation resulted from overprogramming and long <inline-formula> <tex-math notation="LaTeX">$\text{T}_{\mathrm {STRESS}}$ </tex-math></inline-formula>; and 3) achieve reliable and 26+ times faster restore operation compared with previous nvFFs. We have fabricated a nonvolatile processor and a test chip with SWT-nvFFs using logic-process ReRAM in a 65-nm CMOS process. Measured results show sub-2-ns termination response time and sub-20-ns chip-level restore time.

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