A formal model for defining and classifying delay-insensitive circuits and systems
暂无分享,去创建一个
[1] Leonard R. Marino,et al. General theory of metastable operation , 1981, IEEE Transactions on Computers.
[2] Marco Hurtado,et al. Ambiguous Behavior of Logic Bistable Systems , 1975 .
[3] Eby G. Friedman,et al. System Timing , 2000, The VLSI Handbook.
[4] David L. Black. On the existence of delay-insensitive fair arbiters: Trace theory and its limitations , 2005, Distributed Computing.
[5] Joseph S. Ullian,et al. Ambiguity in context free languages , 1966, JACM.
[6] Charles E. Molnar,et al. Anomalous Behavior of Synchronizer and Arbiter Circuits , 1973, IEEE Transactions on Computers.
[7] Jan L. A. van de Snepscheut,et al. Trace Theory and VLSJ Design , 1985, Lecture Notes in Computer Science.
[8] Charles L. Seitz,et al. Self-Timed VLSI Systems , 1979 .
[9] Seymour Ginsburg,et al. The mathematical theory of context free languages , 1966 .
[10] Jeffrey D. Ullman,et al. Formal languages and their relation to automata , 1969, Addison-Wesley series in computer science and information processing.
[11] Alain J. Martin,et al. A Delay-insensitive Fair Arbiter , 1985 .