Virtual shared memory architecture for inter-task communication in partial reconfigurable systems

This paper presents a virtual shared memory architecture for inter-task communication in partial reconfigurable systems. The hardware tasks communicate with each other using the same content shared by physically separated Block RAMs (BRAMs). The coherence of the content is ensured by the Internal Configuration Access Port (ICAP), rather than conventional on-chip logic. The benefit of this approach resides in the flexibility of partial task reconfiguration that results from the ICAP-based synchronization mechanism, allowing hardware tasks to behave like software tasks, as they can be swapped in/out of the chip arbitrarily without any area boundary constraints. Moreover, a fast synchronization method which uses compressed bitstream is presented in this paper. The result shows significant improvements in synchronization speed at a low area overhead.

[1]  Fabrizio Ferrandi,et al.  Caronte: a complete methodology for the implementation of partially dynamically self-reconfiguring systems on FPGA platforms , 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

[2]  Tughrul Arslan,et al.  Efficient On-Chip Task Scheduler and Allocator for Reconfigurable Operating Systems , 2011, IEEE Embedded Systems Letters.

[3]  J. Lockwood,et al.  Dynamic hardware plugins in an FPGA with partial run-time reconfiguration , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[4]  Tughrul Arslan,et al.  Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[5]  Scott McMillan,et al.  A lightweight approach for embedded reconfiguration of FPGAs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[6]  Gordon J. Brebner,et al.  A Virtual Hardware Operating System for the Xilinx XC6200 , 1996, FPL.

[7]  Mikel Azkarate-askasua,et al.  R3TOS: A reliable reconfigurable real-time operating system , 2010, 2010 NASA/ESA Conference on Adaptive Hardware and Systems.

[8]  Mikel Azkarate-askasua,et al.  A Roadmap for Autonomous Fault-Tolerant Systems , 2010, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP).

[9]  Tobias Becker,et al.  Modular partial reconfigurable in Virtex FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[10]  Russell Tessier,et al.  FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..