NISD: A Framework for Automatic Narrow Instruction Set Design

Code size is becoming an important design factor in the embedded domain. To deal with this problem, many embedded RISC processors support a dual-width instruction set. Mixed code generation is also introduced in expectation of achieving both higher code density from the narrow instruction set (usually 16 bits) and good performance from the normal one (usually 32 bits), with little extra cost. To a certain application domain, processors can combine an efficient general purpose instruction set and a narrow instruction set tailored to the particular applications. Since the design of instruction set is highly related to the compiler and the application programs, a feedback driven technique will be a good choice. In this paper, we introduce a framework of automatic narrow instruction set design. The instructions are described in our Instruction Set Description Template (ISDT). Given a set of application programs, the design tool will iteratively use the suggested narrow instruction set represented in ISDT to do mixed-code generation and to update the narrow instruction set according to the evaluation feedback, thus to get an ultimate fine narrow instruction set without human designer's involvement. We describe our method in detail by example of designing narrow instruction set for UniCore with the mediabench as the application set, and show its usefulness through the experiments.