Clustering-based failure triage for RTL regression debugging
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[1] Kwang-Ting Cheng,et al. RTL Error Diagnosis Using a Word-Level SAT-Solver , 2008, 2008 IEEE International Test Conference.
[2] Gábor J. Székely,et al. Hierarchical Clustering via Joint Between-Within Distances: Extending Ward's Minimum Variance Method , 2005, J. Classif..
[3] Igor L. Markov,et al. Automatic error diagnosis and correction for RTL designs , 2007, 2007 IEEE International High Level Design Validation and Test Workshop.
[4] Rolf Drechsler,et al. Debugging sequential circuits using Boolean satisfiability , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[5] David Tcheng,et al. GoldMine: Automatic assertion generation using data mining and static analysis , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[6] Andreas G. Veneris,et al. Path directed abstraction and refinement in SAT-based design debugging , 2012, DAC Design Automation Conference 2012.
[7] Christopher M. Bishop,et al. Pattern Recognition and Machine Learning (Information Science and Statistics) , 2006 .
[8] Masahiro Fujita,et al. A Formal Approach for Debugging Arithmetic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Nasser M. Nasrabadi,et al. Pattern Recognition and Machine Learning , 2006, Technometrics.
[10] Sean Safarpour,et al. Managing verification error traces with Bounded Model Debugging , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[11] Andreas G. Veneris,et al. Simulation and satisfiability guided counter-example triage for RTL design debugging , 2014, Fifteenth International Symposium on Quality Electronic Design.
[12] Andreas G. Veneris. Fault diagnosis and logic debugging using Boolean satisfiability , 2003, Proceedings. 4th International Workshop on Microprocessor Test and Verification - Common Challenges and Solutions.