Experimental and modelling thermal study of a 3D-stacked silicon based LEDs array concept

This work deals with an overall concept of a 3D-stack enabling to produce a directly pluggable high voltage power LED. Using a dedicated silicon vehicle test, a thermal study is carried out with an extensive thermal modelling, optimization, assembly process and Infrared thermal characterization. It is shown that the main thermal issues are due to the presence of the flip chip interconnection layer and in particular the interconnect bump distribution leading to hot spots localization when bumps are missing. According to the results and with a two-steps modelling approach, we can conclude on the good model accuracy (within 11% for the worst cases). Consequently, its relevance for further generation of 3D stacked power devices design highlights the packaging strategy importance to target high performance devices.