FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation

Large area/delay/power overheads are required to support the reconfigurability of field-programmable gate arrays (FPGAs). We proposed a hybrid CMOS/nanotechnology dynamically reconfigurable architecture, called NATURE, earlier to address this challenge. It uses the concept of temporal logic folding and fine-grain (i.e., cycle-level) dynamic reconfiguration to increase logic density and save area. Because logic folding reduces area significantly, most of the on-chip communications become localized. To take full advantage of localized communications, we then presented a new CMOS-based fine-grain dynamically reconfigurable (FDR) architecture. It consists of an array of homogeneous logic elements (LEs), which can be configured into logic or interconnect or a combination of both. FDR eliminates most of the long-distance and global wires, which occupy a large amount of area in conventional FPGAs. FDR improves the area-delay product by an order of magnitude relative to conventional architectures. In this paper, we present an augmented FDR 2.0 architecture, where: 1) the LE is augmented with dedicated carry logic to facilitate arithmetic operations; 2) diagonal direct links are incorporated to improve the flexibility of local communication; and 3) coarse-grain blocks, including embedded memories and digital signal processing (DSP) blocks, are added to support fast data-intensive computations. Experimental results show that the coarse-grain design can improve circuit performance by 3.6× compared with the fine-grain FDR architecture. Incorporation of the DSP blocks in FDR 2.0 also enables more effective area-delay and power-delay tradeoffs, allowing the users to trade performance for smaller area or power consumption. We have implemented the design in the 22-nm FinFET technology, which enables more flexible and effective power management. Finally, different types of FinFETs and power management techniques have been explored in FDR 2.0 to optimize power.

[1]  Niraj K. Jha,et al.  Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Niraj K. Jha,et al.  FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing , 2009, 2009 IEEE International Conference on Computer Design.

[3]  Anish Muttreja,et al.  CMOS logic design with independent-gate FinFETs , 2007, 2007 25th International Conference on Computer Design.

[4]  Wei Zhang,et al.  Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture , 2010, JETC.

[5]  Jonathan Rose,et al.  Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[7]  Srivaths Ravi,et al.  Satisfiability-based test generation for nonseparable RTL controller-datapath circuits , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  André DeHon,et al.  Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density , 1996 .

[9]  B. Nikolic,et al.  FinFET SRAM with Enhanced Read / Write Margins , 2006, 2006 IEEE international SOI Conferencee Proceedings.

[10]  Niraj K. Jha,et al.  Hierarchical test generation and design for testability methods for ASPPs and ASIPs , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Wei Zhang,et al.  A hybrid nano/CMOS dynamically reconfigurable system—Part I: Architecture , 2009, JETC.

[12]  Niraj K. Jha,et al.  Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology , 2011, 2011 12th International Symposium on Quality Electronic Design.

[13]  Srivaths Ravi,et al.  Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications , 2003, ICCAD 2003.

[14]  Wei Zhang,et al.  A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Wei Zhang,et al.  A hybrid Nano/CMOS dynamically reconfigurable system—Part II: Design optimization flow , 2009, JETC.

[16]  Niraj K. Jha,et al.  3D vs. 2D analysis of FinFET logic gates under process variations , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[17]  Niraj K. Jha,et al.  CACTI-FinFET: An integrated delay and power modeling framework for FinFET-based caches under process variations , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[18]  E.J. Nowak,et al.  Turning silicon on its edge [double gate CMOS/FinFET technology] , 2004, IEEE Circuits and Devices Magazine.

[19]  Shekhar Y. Borkar,et al.  Design perspectives on 22nm CMOS and beyond , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[20]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[21]  Wei Zhang,et al.  Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture , 2009, JETC.

[22]  Wei Zhang,et al.  SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Kenneth B. Kent,et al.  The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.