An ultra low voltage ultra low power folded cascode CMOS LNA using forward body bias technology for GPS application

A fully integrated low noise amplifier suitable for ultra-low voltage and ultra-low-power GPS applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S<inf>21</inf>) of 17.6 dB with a noise figure of 3 dB, while consuming only 960μW dc power with an ultra low supply voltage of 0.45 V. The power consumption figure of merit(FOM<inf>1</inf>) and the tuning-range figure of merit(FOM<inf>2</inf>) are optimal at 18.33 dB/mw and 8.8(v·mw)<sup>−1</sup>, respectively.

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