Space Eecient Neural Net Implementation

We show how eld-programable gate arrays can be used to eeciently implement neural nets. By implementing the training phase in software and the actual application in hardware, connicting demands can be met: training beneets from a fast edit-debug cycle, and once the design has stabilized, a hardware implementation results in higher performance. While neural nets have been implemented in hardware in the past, larger digital nets have not been possible due to the real-estate requirements of single neurons. We present a bit-serial encoding scheme and computation model, which allows space-eecient computation of the sum of weighted inputs, thereby facilitating the implementation of complex neural networks.