Efficient FPGA-based Architectures of Finite Alphabet Iterative Decoders for Flash Memories

We present finite alphabet iterative decoders (FAIDs) for hard-decision decoding and 2-bit precision softdecision decoding of column-weight-four low-density paritycheck (LDPC) codes which are applicable for flash memories, and discuss their hardware implementations on FPGA. We show that 3-bit FAIDs provide superior error-rate performance in the error floor compared to 4-bit and 5-bit offset-min-sum decoders while providing significant savings in resource usage for the same achievable throughput. A vertical-layered decoder architecture is implemented for the decoder comparisons, and the FPGA synthesis results are provided for a code rate of 0.94 and 1KByte length quasi-cyclic code.