Semi-analytical modeling of high performance nano-scale complementary logic gates utilizing ballistic carbon nanotube transistors

Abstract Carbon nanotube field effect transistors (CNTFETs) have gained remarkable attention in modern fields, as one of the promising candidates for replacing conventional MOSFETs technology at the end of the roadmap. In this regard, this article presents high-performance complementary logic gates based on ballistic gate-all-around CNTFETs utilizing a novel improved analytical model. This is done by considering the effects of carrier density, quantum capacitance, and the number of channels, which are highly suitable for logic applications. For this purpose, the polarities of CNTFETs are switched between n- and p-type by harnessing its geometrical properties (i.e. the dielectric materials). In the present paper the semi-analytical method is utilized to design complementary logic gates including inverter, AND, and XOR. To benchmark the structure, the main parameters including propagation delay, power delay product, noise margin, and static and dynamic power consumptions are calculated. Then appropriate values are achieved and then used in a simple half adder. It is shown that by applying a small external voltage in the order of 0.8′ V, the enhanced design metrics including static and dynamic powers can be achieved as Ps = 25.12 pW, and Pd = 40.62 nW, respectively. To verify the obtained results, they are compared with those of numerical and experimental models. Our results highlight the use of complementary gate-all-around CNTFET transistors as a promising platform for computing applications.

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