Design of optimized reversible binary adder/subtractor and BCD adder

Reversible logic has gained the interest of many researchers due to its applicability in emerging low power technologies such as Quantum computing, QCA, optical computing etc., Adders/Subtractors are basic design components of any processor. Optimized design of these adders results in efficient processors. In this work we propose optimized Binary adders/subtractors and BCD adders. The adders/subtractors designed in this work are optimized for Quantum cost and Delay. We also propose a generic design of n-bit adders and subtractors. In this work, we explore the use of Negative control lines for detecting overflow logic of BCD adder which considerably reduces Quantum cost, delay and gate count which result in high speed BCD adder with optimized area which give way to lot of scope in the field of reversible computing in near future.

[1]  Robert Wille,et al.  Exploiting Negative Control Lines in the Optimization of Reversible Circuits , 2013, RC.

[2]  Muhammad Mahbubur Rahman,et al.  Synthesis of Fault Tolerant Reversible Logic Circuits , 2009, 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis.

[3]  Robert Wille,et al.  Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines , 2012, 2012 IEEE 42nd International Symposium on Multiple-Valued Logic.

[4]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[5]  Yasuhiro Takahashi,et al.  Quantum addition circuits and unbounded fan-out , 2009, Quantum Inf. Comput..

[6]  Robert Wille,et al.  Optimizing DD-based synthesis of reversible circuits using negative control lines , 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

[7]  N. Ranganathan,et al.  Design of efficient reversible logic-based binary and BCD adder circuits , 2013, JETC.

[8]  H. R. Bhagyalakshmi,et al.  Optimized reversible BCD adder using new reversible logic gates , 2010, ArXiv.

[9]  Chien-Cheng Tseng,et al.  Quantum full adder and subtractor , 2002 .

[10]  Ahsan Raja Chowdhury,et al.  Design of a compact reversible binary coded decimal adder circuit , 2006, J. Syst. Archit..

[11]  Parag K. Lala,et al.  A novel approach for on-line testable reversible logic circuit design , 2004, 13th Asian Test Symposium.

[12]  Rolf Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[13]  Yasuhiro Takahashi,et al.  A linear-size quantum circuit for addition with no ancillary qubits , 2005, Quantum Inf. Comput..

[14]  Majid Haghparast,et al.  Design and Optimization of Reversible BCD Adder/Subtractor Circuit for Quantum and Nanotechnology Based Systems , 2008 .

[15]  K. V. Ramanathan,et al.  Quantum-information processing by nuclear magnetic resonance: Experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system , 2002 .

[16]  Ahsan Raja Chowdhury,et al.  Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[17]  Ashis Kumer Biswas,et al.  Efficient approaches for designing reversible Binary Coded Decimal adders , 2008, Microelectron. J..

[18]  Keivan Navi,et al.  MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT , 2009 .

[19]  Robert Glück,et al.  Optimized reversible binary-coded decimal adders , 2008, J. Syst. Archit..

[20]  B. Parhami,et al.  Fault-Tolerant Reversible Circuits , 2006, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers.

[21]  John P. Hayes,et al.  Advanced modeling of faults in Reversible circuits , 2010, 2010 East-West Design & Test Symposium (EWDTS).

[22]  Thomas G. Draper,et al.  A new quantum ripple-carry addition circuit , 2004, quant-ph/0410184.