A High-Speed, Non-Linear Control Based Voltage Droop Mitigation Technique for Integrated Voltage Regulators in Modern Microprocessors

Modern microprocessors impose stringent constraints on power supply design. Large voltage droops caused by the high output current slew rate (di/dt) requirements of advanced microprocessor features are one of the significant challenges for power supply design. Fully Integrated Voltage Regulator (FIVR) technology introduced in Intel® 4th generation CoreTM processors, features a fast output supply ramp rate by virtue of its small on-die output capacitance. While this provides several benefits, it limits FIVR’s ability to handle high-current workloads and can cause large voltage droops, adversely impacting microprocessor performance. This paper presents a novel non-linear control (NLC) based droop mitigation technique that can reduce output voltage droop by 25% for AVX workloads. The NLC loop works in tandem with the main FIVR loop and kicks in only in the event of a voltage droop larger than a programmed threshold.